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LSI Logic DSP core capable of superscalar functions

Posted: 25 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lsi logic? zsp? zsp500? zsp600? digital signal processor?

Leveraging a three-legged delivery model, LSI Logic Corp. has rolled out the second generation of its successful ZSP open-architecture superscalar DSP cores.

Featuring an enhanced instruction set and user-configurable memory, the ZSP500 can be delivered as a licensable core, ASIC or off-the-shelf chip, targeted at wireless, consumer electronic, and broadband applications.

The 400MHz core was built with high-speed libraries in a 0.135m process of Taiwan Semiconductor Manufacturing Co. (TSMC). A 500MHz, quad-MAC, binary-compatible companion core, dubbed the ZSP600, is slated for licensing in Q1 of 2003 and targets the infrastructure side.

Performance aside, much of LSI Logic's strength lies in its delivery model. "We are the only licensable-core vendor to offer three-way access," said Steve Brightfield, senior IP licensing manager at LSI Logic. "Off-the-shelf standard products, ASIC hard macros to rapidly develop DSP ASICs and, finally, we license a Verilog RTL version."

Independent benchmarking by Berkeley Design Technology Inc. (BDTI), a DSP-technology analyst and software development house, put the ZSP500 ahead of all other cores and standard products now on the market for many of its target apps.

However, it is the business model that really sets the core apart, said BDTI GM Jeff Bier. "We can talk a lot about the architecture, but much of the ZSP's attraction resides in the fact that LSI offers it as a licensable core."

LSI Logic had "a couple of things pulling at this core's design," Brightfield said. "DSPs are becoming more application-specific, and at the same time the demand for code density and cost/performance is also increasing. These are not easy to do at the same time. We focused on scaling clock speed, maintaining dense code and still providing the flexibility of custom instructions."

Power, size, cost range

To meet the disparate requirements of various applications in terms of power, size, cost and processing speed, the dual-multiply-accumulate (MAC) core is scalable on a TSMC process from 100MHz, 1.4mm2, and 18mW to 400MHz, 3mm2, 150mW.

The core is software-compatible with LSI Logic's four-issue dual-MAC ZSP400, which was introduced in 1998. That core was itself based on LSI's G1 instruction set, which has been around since the company's founding.

For the ZSP500, LSI Logic added to the G1 instruction set such features as conditional execution, bit-manipulation functions, enhanced stack support and ANSI-C-like instructions in the compiler for more-efficient code generation, and relabeled it the G2.

"We have been working on this core for two years," said Brightfield. "Our focus was on a balance of performance and power." To facilitate that, the designers opted for a core with six parallel execution units with four instructions per clock cycle for optimal computation and parallelism capabilities. Two of those execution units are built into the load/store units for address generation.

"We got feedback from customers and added acceleration to speed functions such as voice coding, as well as extra instructions for Viterbi error correction," said Brightfield. The core also supports up to 64 external acceleration coprocessors, each "very tightly coupled to the pipeline - to the extent that it is really considered part of the flow," said Brightfield.

Integral to the architecture, he went on, are 64 user-configurable instructions for application-specific acceleration functions. "What we did not want to do was crowd the instruction set with instructions that would have only one application," Brightfield said.

"We needed to maintain the 16-bit instruction-set architecture to keep the code density, which affects the price point. Also, adding instructions takes more op-codes and would force us to go to a larger word size, which would make us less competitive," he added.

The memory architecture is also user-configurable between unified or Harvard, and can be Flash-, SRAM-, or DRAM-based.

Multilevel approach

For power management, which remains essential for mobile applications, the ZSP500 uses a multitier approach. At the most basic level are user-controlled functions such as sleep and power down.

Next comes automatic control at a functional level, managed by the scheduler that powers individual blocks up and down as they are used. Then, at the block level, each execution unit (multiplier, adder, shifter, logic) can be powered up or down using the pipeline logic. Finally, at the implementation level, come features such as clock gating.

Along with the advanced architectural features and flexibility, LSI Logic included a 6.4GB internal bus with bypass logic to balance data flow with the execution units. A standard application programming interface allows outsourcing of firmware, while LSI Logic's open API makes it possible to use off-the-shelf application software.

BDTI's Bier sees LSI Logic's delivery model as the core's real strength and differentiator. Spinning out the core in three ways means cost-driven applications can get off the ground quickly with an off-the-shelf chip, said Bier. The core can then be optimized over time and developed into an ASIC to be manufactured by LSI. Finally, for large volumes, customers can license the core, design their own chips around it and use an external foundry.

In addition, the ZSP500 will be available next year for incorporation into LSI Logic's recently announced Rapid-Chip program. "This is an intermediate step between a full-custom standard-cell solution and an FPGA solution," said Brightfield.

The program essentially takes standard-cell technology and provides it to customers as "slices" - standard-cell definitions of a high-complexity hard macro such as CPUs, memories and complex I/Os. "Around those are uncommitted logic arrays that can be used with just metallization to interconnect these large blocks together," Brightfield said.

On a pure-performance basis, BDTI's Bier found the ZSP500's strengths to lie in the realm of least-mean-square adaptive filters, vector maximum searches, Viterbi and bit-unpack benchmarks. "These are functions that have more going on than simple multiply/accumulate," he said.

Based on the benchmarks, Bier sees "good potential" for mobile applications, "particularly for those that do not have really complex, non-DSP-related control software."

- Patrick Mannion

EE Times

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