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Teradiant samples 40Gbps network processor

Posted: 25 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:teradiant? terapacket? multiservice packet engine? multiservice traffic manager? packet processor?

The TeraPacket chipset from Teradiant Networks Inc. consists of the company's Multi-Service Packet Engine (MPE) and Multi-Service Traffic Manager (MTM), allowing the device to provide speeds of 10Gbps, 20Gbps, and 40Gbps wire-speed performance.

Suitable for use in the design of line cards in Internet routers, multiservice switches, and metropolitan switches used in edge and core networks, the chipset uses a flexible super-pipelined architecture that is fully-configurable with 40Gbps of full-duplex, deterministic wire-speed bandwidth at full QoS.

According to the company, the product also uses a new memory architecture that reduces overall memory size, chip count, cost and power consumption. The architecture uses on-chip RAM and CAM, and optimizes memory bandwidth and capacity utilization through the use of shared memories across all ports.

The chipset is designed to handle all the major communication protocols, including IPv4, IPv6, ATM, Frame Relay, PPP, Ethernet, MPLS, and MPLS Martini Draft.

The 40Gbps, full-duplex, TeraPacket solution uses two TN400 MPEs and two TN401 MTMs, while the 20Gbps solution consists of one TN200 MPE and one TN201 MTM chip. A 10Gbps, full-duplex solution consists of one TN100 MPE and one TN101 MTM chip.

The MPE uses the SPI-4.2 interface to accept HDLC, Ethernet, Frame Relay, and ATM packets from a framer chip. The packets are then processed through the blocks consisting of Link Layer decapsulation, tunnel decapsulation, packet classification, route lookup, policing, and marking.

The ingress packets are then forwarded via the SPI-4.2 interface to the MTM, while the egress packets (i.e. traveling from MTM back to framer) follow a path through similar blocks without packet classification or route Lookup.

The MTM uses the SPI-4.2 interface to accept packets from the MPE, and are then processed through the blocks of congestion control/queue selection, buffer management, and memory control.

The ingress packets are then forwarded via the SPI-4.2 or NPF-SI interface to the switch fabric circuit. The egress packets (i.e. traveling from switch fabric back to MPE) follow a path through similar blocks.

Along with the processor, the company is also offering development tools for the chipset including a simulation engine called CASE (cycle-accurate simulation environment) that enables networking system designers to create real-world simulations of their system designs before deploying a Teradiant chipset in their system.

A software development kit provides the device drivers and APIs for the Teradiant chipset to allow integration of third-party high-level protocol stacks and control plane software. The company also provides a 20Gbps reference board with one OC-192 channel and four OC-48 channels, as well as schematics and complete documentation.

The TeraPacket chipset family will be sampling in December and comes in an FC-BGA package.

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