Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Amplifiers/Converters
?
?
Amplifiers/Converters??

Intel develops 3D transistor design

Posted: 27 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:tri-gate transistor? 3d transistor? moore law? flat transistor?

Intel researchers have developed a 3D "tri-gate" transistor design that is expected to perform better than traditional planar (flat) transistors. This development provides the first glimpse of a new era of non-planar 3D transistor designs that Intel and the rest of the semiconductor industry will implement to maintain the pace of Moore's Law beyond this decade.

Intel's tri-gate transistor employs a 3D structure, like a raised, flat plateau with vertical sides, which allows electronic signals to be sent along the top of the transistor and along both vertical sidewalls as well. This in effect, triples the area available for electrical signals to travel without taking up more space.

"Our research shows that below 30nm, the basic physics of the flat, single-gate planar transistor leaks too much power to meet our future performance goals," said Dr. Gerald Marcyk, director of the Components Research Lab at Intel. "The tri-gate transistor design will allow Intel to build ultra-small transistors that achieve high performance with low power and continue driving the pace of Moore's Law."





Article Comments - Intel develops 3D transistor design
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top