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Startup to open RTL-to-test bridge

Posted: 01 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:rtl? atpg? bist? xlator? stridge?

Aiming to move test to the RTL, engineer Nikhil Dakwala is preparing a tool that he calls the industry's first memory RTL-to-ATPG modeling "bridge." The Xlator is the first off-the-shelf product of Stridge Inc., Dakwala's one-man consulting firm.

"My goal is to make it easy for designers to use test tools," Dakwala said. "What I want to do is build bridges that allow them to perform RTL sign-off." Today, he noted, designers must build memory ATPG and BIST models by hand in order to run gate-level ATPG or BIST tools. Xlator, he said, makes it possible to do this modeling automatically at the RTL.

A test engineer since 1991, Dakwala has done a lot of memory ATPG and memory BIST modeling himself. He has worked for such companies as Motorola, Ross Technology and IBM. He started his consulting practice in January 2000 and incorporated Stridge earlier this year.

"Customers all need to run ATPG these days, and most chips have memories," Dakwala said. "SoCs may have hundreds of small memories. If you model all those by hand, it will take a long time and by the time you reach the gate-level, it may be too late to make changes."

Memory BIST, he said, requires its own set of models, which are different from the ATPG models. Xlator supports both ATPG and BIST modeling.

Xlator takes in Verilog RTL netlists. There are some coding requirements, but they involve nothing more than good coding practices, he said. The tool does not work well with mixed RTL and gate-level netlists.

The output is an ATPG model that can be fed into Mentor Graphics Corp.'s FastScan tool and a BIST model that can be fed into Mentor's MBIST Architect. Those are the only test tools supported at the moment, but Dakwala said he plans to support tools from other vendors in the future, and also to support VHDL.

After using Xlator, designers synthesize logic to the gate-level. Then, ATPG or BIST can be applied across the entire design, with no need for a manual translation to gates. If needed, users can change the RTL model and rerun the entire flow.

Xlator is now in alpha testing and a production release is expected this quarter. In the meantime, Dakwala is paying the bills via consulting contracts with ARM, Motorola, Sigmatel, Agere and other customers.

Dakwala wants to expand his company, hire more personnel and become a commercial EDA vendor. In addition to supporting more test tools, he'd like to build other bridges, such as an analog ATPG and BIST modeling tools.

- Richard Goering

EE Times





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