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Mentor revamps tool set for analog IC design

Posted: 01 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:IC design tool? adms? simulation engines? soc design? eldo?

In a dramatic effort to reposition itself against the incumbent in the analog tools world, Mentor Graphics Corp. is enhancing its front-to-back (top-down/bottoms-up) tool set for analog IC design. Called ADvance MS (ADMS), the tool set incorporates all high-level languages, advanced circuit simulators, as well as layout and verification tools, complete with parasitic extraction, schematic comparison and back annotation.

Mentor believes that the new package will offer language support and fast simulation to new-generation SoC designs incorporating analog and RF peripherals, as well as processors and memory. These designs include digital SoCs with a dominant amount of analog circuitry (called "Big A; little d"), as well as digital designs with a small amount of analog ("Big D; little a").

"DSP communications devices, for example, once included a little bit of analog," said Wally Rhines, Mentor president and CEO. "They are now including more and more analog on the chip," he said.

These integrated analog blocks include ADCs and DACs, PLLs, RF modules, and adaptive filters. The ADMS design flow gives SoC designers the ability to examine performance at the highest level--in advance of pushing each block through its own flow. At final chip assembly, ADMS tools will complete functional verification at the full-chip level.

At the heart of the ADMS tool set is a single-kernel, language-neutral simulator that combines four high-performance simulation engines in one tool: Eldo for general-purpose, large-signal model simulations; ModelSim for digital simulations; Mach TA for fast transistor-level simulations and Eldo RF for modulated steady-state simulation.

The glamour item is Mach TA. Mentor's Eldo simulator, which would automatically partition circuits between MOS transistors that can be modeled with relaxation algorithms and full-feedback circuits requiring more rigorous mathematical modeling, had always claimed to run faster than conventional Spice. Though Mach TA can also take a standard Spice netlist as its input, it is an entirely different modeler, Rhines insisted. It is 1,000 times faster - three orders of magnitude - and still provides accuracy to within 3 percent of Spice, he said. For full-chip, transistor-level simulation, the Mach TA simulator offers users the ability to trade accuracy for speed, Rhines said.

To be sure, the Eldo RF option adds both harmonic balance and time-domain simulation to the ADMS package. Built upon the Eldo analog simulator, Eldo RF includes algorithms specifically geared toward RF ICs operating in the GHz range. Applications for the modeler include transceiver components like low-noise amplifiers, mixers and voltage-controlled oscillators. With Eldo RF integrated in the ADMS simulation environment, ADMS uses a modulated steady-state analysis algorithm to model digitally modulated RF signals.

Full-chip verification

With Calibre xRC, Mentor applies its core Calibre extraction technology to the specific requirements of analog/mixed-signal design. Traditionally, parasitic extraction has forced SoC designers to harness a small arsenal of tools. In the analog/mixed-signal IC design flow, Calibre xRC can replace this unwieldy lot with a single multipurpose tool.

The product provides parasitic extraction for a full-chip, digital circuit extraction and back annotation - complete with naming conventions, said Rhines. "None of the extractors go down to the transistor level," he added. "This one will do it."

The ADMS tool set provides high-level language support, including verification support for Verilog AMS. The design flow uses a single netlist hierarchy that allows designers to freely combine VHDL, Verilog, VHDL-AMS, Verilog-AMS, Spice and C anywhere in the design. This enables both top-down design and mixed-level simulation for bottom-up verification.

The tool set includes the Design Architect-IC tool (an SoC design "cockpit") and the IC Station chip assembly solution, for physical layout, top-level floor planning and routing. It runs on Linux, HP and Sun platforms and even talks to the Cadence Analog Artist Environment.

"Deep-submicron design is where mixed-signal design becomes real. You need to integrate it and not throw it over the wall."

- Stephan Ohr

EE Times

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