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TI India develops ASIC cell design methodology

Posted: 04 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC cell design? eSpec methodology? ptv? espec? alf?

Engineers at Texas Instruments India have developed a new specification method for driving cell design flow, overcoming the current lack of a set process for specification capture in ASIC cell design methodology. Using the methodology dubbed eSpec, designers will be able to spend more time on actual cell design to deliver better libraries, the company said.

Three engineers who authored a paper on the new methodology - Narasimha Murthy, Poorvaja Ramani, and P.S. Vijay Kumar - said designing to specifications is a key issue for cell designers, since there is no defined process for doing so at present.

Among the problems that lack of a standard process now creates are subjective interpretations of cell functionality; redundant and inconsistent data views for different work flows; and the absence of proper check mechanisms. Those missing elements affect the quality of libraries at the expense of designers' valuable time.

The eSpec methodology addresses those problems by segregating specifications into technology-dependent and -independent vectors. "It prescribes capturing functional specification in Verilog and the library, cell characteristics in the newly devised eSpec format. This extensible format allows hierarchical specification across library, cell groups and cells and allows overriding across these levels," the authors noted.

The need for more complex functionality means extra analysis and painstaking design for ASIC cell designers. The authors said key issues for cell design flow include fuzzy functionality interpretation. An example is the description of functionality in e-mails and notes, leading to subjective interpretations of functionality among cell designers and model developers.

Error-prone tasks

Since characterization input databases have a library-specific view, data for a particular cell gets distributed in different files, making file synchronization difficult. Many repetitive tasks must be performed manually, like entering process, temperature and voltage (PTV) conditions and slews on a huge number of cells. Such tasks are therefore prone to errors.

The authors said that given the number of times PTV changes are made to libraries for a specific technology, a single PTV change for a single characterization view like timing needs more than 300 files to be edited in a library of reasonable size, often requiring another parallel-input database.

The eSpec is structured based on the key classifications of input data, such as library, cell group, and cell specific. Based on those, the eSpec components include customer, executable, product, design, and technology-dependent and technology-independent specs.

A format for eSpec was drawn up with simplicity and intuitiveness in mind, as well as the possibility of it becoming an industry standard. Designers have a choice of specifying data logically in any of the eSpec entities, and overrides are allowed across those files. It is also designed to eliminate data redundancy and allow for extensibility and data reuse so that data can be retrieved without bottlenecks.

The eSpec format was created, the authors said, by addressing the non-usability issues posed by the Advanced Library Format and the Synopsys Liberty Format.

The eSpec methodology relies on the ALF approach and is based on the object model. The format requires specifying various objects, their annotations and the relationship among them.

The new cell creation flow enabled by eSpec is being deployed in phases and is now being used to develop ASIC libraries, the authors said. Benefits are expected to include reduced cycle time and higher quality of components, allowing designers to spend more effort on better design and analysis.

The researchers said future work would focus on creating more utilities to create or validate eSpec. They also plan to expand the format to capture specifications for analog and memory cells, developing a new vector-generation flow for complex cells and a robust design analysis flow.

- K.C. Krishnadas

EE Times





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