Broadcom rolls out 4.8Gbps IPsec processor with AES feature

Broadcom Corp. has introduced the BCM5841 IP security (IPsec) processor that incorporates Advanced Encryption Standard (AES) support with 256-bit key processing and proprietary packet load-balancing technology, delivering security encryption, and authentication at multi-Gigabit speeds in VPNs.

The BCM5841 can also be used as an IPSec coprocessor that can computationally offload demanding cryptographic operations from a host protocol processor.

The packet load balancing feature allows networks to maintain full performance on a single flow and is designed to maintain its performance on all packet sizes without performance degradation. This enables the processor to handle processing-intensive workloads and the typical mix of traffic generated by enterprise and carrier-class networks that transport voice, video and data, regardless of packet size or the number of connections.

A member of the company's CryptoNext product portfolio, the BCM5841 features flexible interfaces supporting either a POS-PHY level 3 interface or a FIFO-configurable interface. The FIFO-configurable interface is used to attach to Broadcom's SiByte family of broadband processors.

It is backward-compatible with the BCM5840 device and uses the API software, making it forward-compatible with the company's next-generation of multi-Gigabit security solutions.

The BCM5841 is available in four different configurations - 4.8Gbps throughput (BCM5841-48), 2.4Gbps (BCM5841-24), 1.2Gbps (BCM5841-12), and 0.6Gbps (BCM5841-6). In all configurations, the chip supports IPSec bulk payload processing for all AES modes, including 128-, 192- and, 256-bit AES-CBC and AES-CTR key length support.

It also supports 3DES and DES symmetric algorithms, as well as HMAC-MD5 and HMAC-SHA-1 hash algorithms. The BCM5841 requires no external components or memory and has a power consumption of 2.8W at 1.8V for 2.4Gbps performance.

Manufactured using a 0.18?m CMOS process, the BCM5841 is available in a 256-pin TBGA package (27-by-27mm) and a 256-pin FPBGA package (17-by-17mm).