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Lightspeed boosts ASIC platform with 0.135m move

Posted: 09 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? standard-cell design? ASIC? SRAM? Lightspeed?

Looking to drive a wedge between FPGAs and standard-cell design, Lightspeed Semiconductor Inc. has given its modular-array ASIC platform a performance boost by sprucing up its architecture and shifting to 0.135m design rules.

As a result, Lightspeed said, logic performance will more than double, rising to 700MHz, compared with 200 MHz for 0.255m products. The move to 0.135m also provides more logic and memory for designers to exploit. The latest platform, called Luminance, will scale from 250,000 to 10 million logic gates and can include 540,000 to 5 million SRAM bits.

On the input/output front, Luminance will support many of the low-voltage differential signaling-based standards running up to 1.244Gbps. Each I/O includes double-data-rate registers needed for interfaces such as HyperTransport, SPI-2, and external DDR DRAM and SRAM.

For certain I/Os that require special expertise, Lightspeed is seeking outside help. Silicon Logic Engineering Inc. will provide an SPI-4 Phase 2 firm macro derived from a netlist for predetermined placement. Lightspeed is also working with analog expert Theo Mulder to incorporate a 3.125Gbps serdes hard core in selected Luminance products. Lightspeed said it will start verifying the serdes core this month, and expects to include it in Luminance products by the second half of 2003.

At the module level, the company said it has improved density and synthesis mapping by adding more device elements to its array of homogeneous macros, including one that contains both sequential and combinatorial functions with test logic and memory.

Xilinx similarities

Lightspeed's architecture may seem familiar, particularly to those who know something about Xilinx Inc.'s FPGAs. Indeed, Lightspeed is making a deliberate attempt to woo designers accustomed to working with the leading FPGA vendor's Virtex 2 devices. Similarities include the SRAM size, I/O banks, and the use of termination resistors.

Even so, there are architectural nuances that set the Luminance apart from FPGAs. The impedance control option, for example, includes a pin through which the outputs can be adjusted, which helps prevent spikes when samples are taken just as impedance changes. There's also no limit to the number of clock trees that can be used, said Michael Sydow, vice president of marketing and applications at Lightspeed.

Lightspeed's architecture also includes innate test capabilities that go well beyond scan insertion, the company said.

And because Luminance is made up of an array of predefined modules, the company can manufacture and stock partially finished wafers and customize them later, allowing it to get a customer from a netlist to production in 21 weeks.

The company is taking designs today and plans to start production runs by the first quarter of 2003.

- Anthony Cataldo

EE Times

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