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Swedish startup eases use of formal tools

Posted: 15 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:safelogic? safelogic verifier? safelogic monitor? verification tool? testbench?

Promising both powerful technology and ease of use, verification startup Safelogic is rolling out a formal property checker and a simulation "plug-in" for property monitoring.

The Safelogic Verifier, a static formal verification tool, and Safelogic Monitor, which allows property-based simulation with the Mentor ModelSim and Cadence NC-Sim simulators, are both based on VHDL and a proprietary property language at present. But Safelogic said it is moving rapidly toward support for Verilog and for the emerging Sugar property-language standard.

"There are many companies offering formal property checkers, but Safelogic's approach is unique," said CEO Hakan Rippe. "We have a really good underlying technology, but we have also focused on usability," he said. "We are making property-based verification tools for the rest of us - not only for early adopters, but easy-to-use tools for a broad audience."

Safelogic was founded in 1999 by Claes Strannegard, whom Rippe described as the first person in Sweden to receive a doctoral degree in mathematical logic. Rippe said the company focused on research for its first 18 months, and then turned its attention to product development. Ericcson is an initial customer.

Safelogic currently employs 18 people and has received European venture-capital funding. There is no U.S. office yet, but the tools can be downloaded from the company's website at, for a 30-day free evaluation.

Rippe, who has been with the company since August, was previously the EVP of business development at software-development tool provider Telelogic.

Rippe said that Safelogic has combined traditional model checking with automatic theorem proving and SAT (satisfiability) solvers. This mix allows the tools to both prove properties and find counterexamples.

Also, he said, the underlying technology avoids the "state space" explosion that affects most other formal tools. Rippe said Safelogic has successfully run its tools on designs with 350,000 gates, and is currently working on considerably larger designs.

Simplicity is also one of the company's claims. With the Verifier product, Rippe said, customers need only provide a RTL VHDL file and write properties, which are represented in a separate file. He said Verifier expects to support Verilog in Q1 of 2003 and that Monitor will support Verilog "within a matter of weeks."

Safelogic's current property language supports some Sugar constructs, "but we cannot say it is Sugar," Rippe said. He noted that Safelogic plans to support all Sugar constructs during the first quarter of next year, but may provide some optional extensions to that language.

Verifier's output is either a proof that the design is satisfying the properties or a counterexample if a property is violated. The counter example comes with a waveform that shows the data sequence that caused the violation.

The Monitor product can use the properties specified in Verifier, but Monitor can also run as a standalone product. Users provide VHDL code and properties, and run simulation as usual. Monitor provides a waveform that shows whether properties are fulfilled or not.

Monitor simplifies the creation of testbenches, Rippe said, because all the user has to provide is the stimulus generation portion of the testbench.

List pricing for Verifier is in the $70,000 to $100,000 range, with Monitor listing at one-tenth the price.

- Richard Goering

EE Times

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