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Tensilica pumps processor

Posted: 16 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:configurable processor cores? xtensa processor? tensilica?

Processor intellectual property (IP) provider Tensilica Inc. has kicked its configurable processor core up a notch by adding new hardware and software features to aid multiprocessor SoC design.

The company said that more than half of its customers already use two or more Xtensa processors per design. Most chips with Tensilica processors use five of these configurable cores per design (the largest number is 18), said Steve Roddy, director of product marketing.

Most are used for different purposes. "Typically there are two to four configurations doing different tasks in the SoC when there are multiple processors," he said.

Naturally, Tensilica is eager to get more customers to use more Xtensa cores per chip design. So last year, it added exploration tools for managing multiple processors, ways to model bus traffic and memory-sharing features to its core.

For its latest Xtensa 5, the company has made improvements to the interface so that the processor can more efficiently interact with other components on the same chip. One of these is a multicycle Xtensa local memory interface that allows more tight-knit communication with application-specific logic and the queues linking different Xtensa processors. This grew out of the need to create a "chain data path" of processors and fixed logic designed for a single task, Roddy said.

Xtensa 5 also includes a DMA engine so that the processors can function as masters or slaves. In this way, the processors are able to reach across more boundaries, speeding data transfers among different elements of the design. Other hardware features added to Xtensa 5 are a write-back cache option which unclogs transaction traffic and boosts bus bandwidth, as well as a special register that gives each processor a unique identity for natively parallel applications.

Aside from the hardware, the company has tweaked its C/C++ compiler to boost performance, in some cases by as much as 50 percent, the company said.

A new user-defined conditional load/store instruction has been added as a way to avoid branch instructions and there are now more instruction extension models to boost the core's frequency.

Based on 0.13m design rules, Xtensa 5 is said to run at 350MHz (worst case) for "typical" configurations. For larger configurations, the core runs at 275MHz (worst case).

- Anthony Cataldo

EE Times





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