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DRAM makers begin march toward DDR-2

Posted: 18 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:double-data-rate dram? ddr? ram chipset? ddr2? rdram?

Prepping for the high-end systems that should appear in 2004, chip vendors are laying the groundwork for next-generation DDR DRAM. But the transition, they said, will depend on their sidestepping some technical and business pitfalls along the way.

The good news is that DRAM makers are singing the praises of DDR-2 in unison - a refreshing change from the DDR-versus-RDRAM wars that bred confusion and squandered resources in recent years. At the Denali Software Inc.'s MemCon conference, Samsung, Elpida, and Nanya showed road maps for DDR-2 that start with introduction this year and a gradual move to volume production in early 2004.

"Design work is well under way at the chipset houses," said Jim Sogas, VP of sales for Elpida Memory Inc. "We have gone past the philosophical phase, and we are in the 'when to make it work' stage."

Next year's Q2 should see the debut of chipsets that support DDR-2 and are backward-compatible with the current DDR generation, said Tom Quinn, VP of marketing at Samsung Semiconductor. "My experience is that you will see chipsets that support both DDR-1 and DDR-2."

Indeed, Denali Software said it has finished a DIMM controller core that will link to both DDR generations. Denali is making the core available for licensing. "All the interest is there from the early adopters trying to get onto it," said Kevin Silver, VP of marketing at Denali.

Memory makers are looking to seed the market with DDR-2 devices this year. Elpida has been selling samples of its first 512Mb DDR-2 chip since July. Samsung and Nanya will follow suit in Q4, executives of those companies said.

While DDR-2 builds on the existing DDR spec, the transition calls for memory vendors and system designers to make some significant changes. For DRAM makers, the biggest change will be moving from 2.5V to 1.8V core voltages, Sogas said.

DDR-2 is not expected to ship in high volumes until early 2004, so some DRAM makers plan to produce stopgap devices based on DDR-1 that will run at 400MHz, or an internal speed of 200MHz. But Sogas said it will be hard to get enough yields of DDR-1 devices with core speeds of 167MHz or above. "You can make them, but you cannot make a lot of them," he said. "That is why from our point of view, it is going to be a narrow market."

400MHz stand-in

That, however, is not stopping companies like Samsung and Nanya from pushing their so-called DDR-400 agendas forward. Samsung expects 20 percent of the DDR chips it makes by Q4 to make the 400MHz speed bin.

Module maker Kingston Technology Inc., for one, recently said it has started making DDR400 dual-in-line memory modules in limited quantities for system builders and PC enthusiasts. The 256MB and 512MB modules were tested on available platforms that support DDR400 and should be ready for volume shipment this Q4, according to the company.

DDR-2 uses a 4-bit prefetch rather than the 2 bits of DDR-1, giving it twice the external bandwidth of DDR-1 for the same internal frequency. With this scheme, DRAM vendors expect to easily hit speeds above 500MHz with their first DDR-2 devices and go up from there. "DDR-2 will enter volume [production] at 533MHz because it can yield there, and the front-side buses will match up," Sogas said.

Still uncertain is how much DRAM makers are willing to invest to make the transition to DDR-2 while demand remains weak. DDR-2 chips are expected to ship at the 512Mb density, which will require that DRAM makers shift to 0.15m design rules as the parts move into full production, Quinn said. Sogas said Elpida is comfortable with its current 0.135m design rules for volume production.

Much to consider

System designers will also have much to consider. DDR-2 will require new motherboards and modules, and designers will have to learn to work with the more demanding tolerances and shorter timing windows of the high-frequency memory chips. "Once upon a time, this was called RF," Sogas quipped.

Even the move to DDR-1 has caused some to take a fresh look at how to connect to system architecture. LSI Logic Corp. said it had to develop a special DDR interface core for its ASIC customers that could handle the faster setup and hold time of DDR as well as phase-shift the data clock by 900. "If we did not have this [interface], then each design would have to go through a very involved layout," said Nilesh Amin, product-marketing manager for storage and computing ASICs at LSI Logic.

For DDR-2, LSI Logic will have to make changes to its interface core and add two more pins to accommodate its differential signaling. And while the DIMM has been defined for PC memory, there are still no standard interface specifications for the point-to-point memory solutions used in networking and graphics applications, Amin said.

- Anthony Cataldo

EE Times

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