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Open-source C compiler targets FPGAs

Posted: 22 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? open-source C compiler? reconfigurable logic? Streams-C? Xilinx Virtex-2000 devices?

Seeking to eliminate the need for detailed hardware expertise for FPGA design, a research group at the Los Alamos National Laboratory (LANL) developed an open-source C compiler for reconfigurable logic. Called Streams-C, the compiler doesn't generally yield the performance of RTL design but claims to boost productivity by 10 to 100 fold.

Streams-C accepts a subset of the C programming language, performs behavioral synthesis, and outputs synthesizable RTL VHDL code. It currently targets Xilinx Virtex-2000 devices on Annapolis Microsystems' Firebird board, but claims to be easily retargetable.

The compiler was developed under Defense Advanced Research Projects Agency funding under the direction of Maya Gokhale, project leader for deployable adaptive processing systems at LANL. Gokhale said she'd been developing compilers since 1988, and wrote a compiler for the Splash machine, one of the first reconfigurable computers.

Then, she came across a new approach - a compiler that relies heavily on parallel processing. "After a few years of looking at the problem, I realized that most of the application space could be described well with a stream-oriented communicating sequential processes model," she said.

The result was Stream-C, which is freely available for research and government purposes, with a commercial licensing process underway. Gokhale said that in addition to LANL, several universities are using the compiler, and EDA companies have expressed interest in commercializing it.

Gokhale said the compiler makes FPGA design available to software engineers, but they should still have an "abstract notion" of hardware. "One way to get performance is to tile application-specific arithmetic units across a chip," she noted. "Telling the compiler to unroll inner loops is a way to do that."

What's not needed, she said, is knowledge on the hardware at a clock cycle level. In fact, Streams-C doesn't provide any access to what's going on at this level. In contrast to SystemC, which provides both behavioral and structural views, Streams-C is purely behavioral. It assigns operations to clock cycles, thus providing behavioral synthesis.

As with most highly automated techniques, there's a performance and area tradeoff for using the compiler. Gokhale said that LANL has run some comparisons to designs done at the register-transfer level by experienced hardware engineers, and found comparisons ranging from "nearly comparable" to one design that had two times the clock frequency and one-fourth the area of the chip generated with Streams-C.

That faster and smaller design, however, was completed by an experienced hardware designer who spent six months optimizing it. Streams-C, in contrast, can get from C to VHDL in "seconds," Gokhale said. "I would say the productivity is like a factor of 10 or 100 over hand-done hardware," she noted.

In addition to design creation, Streams-C comes with a simulator. "You can simulate the logic of the parallel program at a functional level, and get rid of a lot of deadlock and livelock conditions," Gokhale said.

Streams-C accepts a subset of C. It includes array records, but doesn't handle generalized pointers. It has pragma extensions that let users assign arrays to different memories. Additionally, the user creates an architecture definition file that describes the target FPGA board.

A shortcoming of pure C is that it doesn't represent concurrency. The notion of concurrency does exist in Streams-C, Gokhale said, but in a different fashion from HDLs. "It's a parallel programming language," she said. "You have an annotation where you say a subroutine is really an independent process. In the main program you initiate each of the processes, and they're concurrently activated."

Streams-C, which runs on Linux PCs, uses the Stanford University Intermediate Format (SUIF) compiler tool set to parse and analyze C programs. Two passes have been added to the SUIF compiler flow - one for analysis and scheduling, another for VHDL generation. It can pipeline inner loops and can unroll loops, and it automatically schedules memory access from external memories.

Gokhale said Streams-C can be targeted to platforms other than Firebird through the architectural definition file. The user would also need to rebuild the FIFOs for the new target FPGA.

While Streams-C is "completely open" for research or government work, Gokhale said LANL is still working out licensing for commercial users. "One of the contributions of this work is that the source code is completely open," she said. "Anybody can look at it and see how to do behavioral synthesis. It's very useful as a teaching tool."

Streams-C is available from LANL's reconfigurable computing web site. That site also offers a library of pipelined, parameterized modules for floating-point operations, a digital receiver library, and Virtex radiation test software.

- Richard Goering

EE Times

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