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Virage to license logic IP

Posted: 23 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:embedded memory? logic libraries? programmable cells? SoC? ASIC?

Virage Logic Corp., best known for embedded memory, is making a full frontal assault into logic IP. The company said it is ready to license logic libraries for both standard cells and metal programmable cells with the planned rollout of the ASAP Logic offerings. They include patented place-and-route routines that increase logic block area utilization by up to 20 percent, the company said.

Virage is now pitching itself as a one-stop shop for embedded memory, logic, and I/O blocks as pressure builds on circuit designers to use predefined IP as SoC building blocks for the sub-130nm era. ASAP for Virage stands for area, speed, and power, the same moniker used for one of the company's successful lines of embedded memories. Virage tipped its hand earlier this year about its logic foray when it bought In-Chip Systems Inc., a small logic-design company with just 15 engineers.

Through the acquisition, Virage started to graft its extensive experience with embedded-memory products to In-Chip's logic savvy. Though small, In-Chip had an impressive list of customers ranging from Epson, Fujitsu and Motorola to NEC, Toshiba, Yamaha and Sony, the last of which included some of In-Chip's IP in the Playstation game consoles.

ASAP Logic standard cells will premiere in a high-density iteration, to be followed by high-speed and ultra low-power cells.

The architecture's layout strategy enables improved pin accessibility and eliminates cell blockage from the power grid, Virage said. It does this by routing the first and second metal layers along the same horizontal axis, instead of along alternating horizontal and vertical axes. That frees up cell access along the vertical axis.

"We get more tracks where we can run signals and therefore drop connector pins, and that increases the pin accessibility and improves routing," said Adam Kablanian, president and CEO of Virage. "It is a key difference to a conventional approach."

When routing power connections, designers will also be able to save on space, Kablanian said, by running power lines within the same cell area instead of adjacent to it. Usually, designers lay out a "metal one" (M1) layer for chip interconnects along a horizontal axis, followed by a "metal two" (M2) layer along the vertical axis. Another M2 layer for power would run next to the cell to avoid shorting out wires.

"That is lost space," said Kablanian, "and the second major difference in our approach" over conventional architectures. In the Virage design, M1 and M2 run horizontally, and in parallel; M2 power straps run along the top and bottom of the cell. In addition, an M3 layer can be added for another power connection. The space savings associated with running the power straps within the same cell space, instead of alongside it, can amount to 20 percent, Kablanian said.

The changes will also improve performance, he said, by allowing engineers to take advantage of shorter signal lengths to use low-power transistors or to increase performance across the chip because of lower capacitance.

Changing metal

Virage will also release its high-speed metal programmable cells today, and then follow up with a high-density version. The configurable cells will allow designers to change logic functions by altering between two and four metal layers. The benefits are similar to gate arrays without the area penalty, Kablanian said, adding that the size closely competes with a fully diffused standard cell. In the 90nm era, where masks will run at least $1.5 million, Kablanian said such flexibility could add up to a six-figure savings.

Virage will target the programmable cells at low- to medium-volume ASIC designs, where all-layer mask changes would otherwise burden the profitability of a design. The standard cells will be pitched for high-volume customers, such as designers of consumer electronics devices, where a small die savings can reap big dividends. For example, a part slated for a million-unit run that saves 10 percent in die area from the ASAP Logic layout could, in a 130nm process, see $1 million to $10 million in savings, depending on chip size, Kablanian said.

More to come

Virage is not the first out of the gate with a collection of building blocks for SoC. LSI Logic Corp., for one, recently announced a similar approach, paired with some design services, in its RapidChip ASIC suite. Others are in the market, too, or thinking about it as the deep-sub-micron era descends upon the industry.

Virage said its advantage lies in a unique, tested design approach that has already been used by high-profile customers. The company said it is also working on ways to evolve the bundle of IP blocks into optimized platforms that target certain applications, such as graphics or communications, or provide higher yields in the rough-and-tumble world of sub-90nm design. Kablanian said the company will stop short of offering design services.

Kablanian would not offer details of the optimization strategy, but said Virage would offer the kind of popular improvements that implementing built-in self-test and repair did for its embedded memories. Clues to the "secret sauce" will be forthcoming over the next few months, he said.

For fabless companies, ASAP Logic will first be accessible on TSMC's 130nm process before migrating to other foundries. The design fee for the high-speed metal programmable cells starts at $50,000; for high-density standard cells, it is $25,000.

- Mike Clendenin

EE Times

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