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LSI Logic extends reach of wirebond packaging

Posted: 24 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:LSI Logic? wire bond packaging? chip? active I/O circuitry? Pad on I/O?

LSI Logic Corp. has developed a form of wirebond packaging that places bonding pads directly on top of a chip's active I/O circuitry. The "Pad on I/O" approach enables significantly smaller die sizes for pad-limited designs done at 130nm and 90nm design rules, and makes possible higher I/O counts in wirebond packaging, LSI Logic said.

The placement of the bonding pad directly on top of the I/O is made more remarkable by low-k dielectrics' tendency to mechanical weakness. A conventional wirebond package places the bonding pad outside of a chip's I/O slots.

The Pad on I/O approach supports two rows of staggered signal interconnects and a third outer row of power and ground connected directly to a die without using I/O slots.

The three rows of connections in Pad on I/O packages will support a 25 percent higher I/O density than conventional wirebond packages, and will be able to support up to 780 signaling pins and more than 200 power and ground connections, said LSI Logic technical marketing manager Stan Mihelcic. Pad pitch can be reduced to 275m, down from 40 5m on conventional wirebond packages.

New designs of cost-sensitive products can expect the Pad on I/O approach to resolve pad-limit problems, extend the life of wirebonding, and cut overall costs, LSI said. High-performance products can also use the approach, the company added.

"By going to a three-row Pad on I/O package we have achieved a 50 percent reduction in the die size for one product, from 10.6mm on a side to 7.6mm," Mihelcic said.

Flip-chip vs. wirebond

To be sure, flip-chip packages will continue to have lower inductance, higher signaling rates and higher I/O densities than wirebond packages. Those attributes have led LSI Logic and other chip makers to extend flip-chip packaging to lower-cost, four-layer plastic substrates.

But the Pad on I/O approach will allow wirebond packages to extend their reach upward as flip-chip packages continue to reach downward, Mihelcic said. Wirebonding may account for only about a third of all 130nm designs at LSI Logic, and the Pad on I/O approach may partially reverse a trend toward flip-chip packages.

Ronnie Vasishta, VP of technical marketing at LSI Logic, said the company realized when working on 0.185m designs that nearly all products would be pad limited at 0.135m and finer design rules. Even as the silicon area required for active circuitry is reduced, the need for an equal or greater number of I/O pads around the perimeter of a die would prohibit a reduction of overall die size without some innovation, Vasishta said.

LSI Logic assigned a team of its packaging engineers - it employs about 40 in-house - to work with suppliers to develop the materials that could support a three-row wirebonding approach. The company no longer owns a packaging prototype line in Fremont, California, but works with outside packaging houses. It will license its Pad on I/O approach to these partners and to packaging subcontractors worldwide. For the Pad on I/O project, major makers of wirebond equipment were contacted to make sure their machines could be adjusted for the force, power, and time parameters that define wirebonding.

LSI Logic has tested the approach on many different designs and has subjected evaluation vehicles to various accelerated thermal stress tests. No evidence was found of opens or shorts, which indicate low-k cracking and material delamination.

"There are no downsides that we have found, and we have designs under way today that will go into production in the middle of next year," Vasishta said. LSI Logic expects that eventually all of its wirebonded products will use the Pad On I/O approach.

- David Lammers

EE Times

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