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Lattice FPGA integrates 3.7Gbps serdes transceiver

Posted: 24 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lattice semiconductor? ort82g5? orso82g5? gdx2? fpga?

Lattice Semiconductor Corp. has rolled out two FPGAs and one switching device that integrate a serdes transceiver, a technology that is taking the programmable-logic world by storm.

The three devices, which are offered in a variety of baud speeds and signal quality ratings, target a wide scope of applications ranging from high-speed backplanes needing maximum signal reach and minimal jitter, to board edge connectors where cost is paramount.

Serdes denotes a class of serialized interconnect schemes in which a chip's clock and data are intertwined rather than separated, enabling higher speeds, fewer signal lines, and longer connections. Other programmable-logic providers are also adding the capability to some of their devices.

At the high end, Lattice has introduced the ORT82G5, an FPGA with 10,400 programmable-logic elements and one million specialized ASIC gates for the serdes interface. Each of the device's eight serdes links can transfer data at 3.7Gbps across 26 inches of an FR-4 backplane over a wide range of temperature and Vdd environments.

Moreover, the company claims the transceiver can generate signals that are clean enough for interconnect standards like Fibre Channel, Infiniband, SFI-5, XAUI, and SONET/SDH.

In fact, the transceiver specifications are above the requirements of most backplanes, said Steven Laub, president of Lattice. "If this was a little bit better we could terminate optical lines," he said.

Distinctive approach

Lattice is fielding different devices for different encoding schemes, an approach that distinguishes it from its serdes-bearing FPGA rival, Xilinx Inc. The ORT82G5, for example, includes ASIC gates for 8b/10b encoding and aggregating channels for standards such as XAUI. But for SONET-based backplanes, Lattice is delivering a separate FPGA device with ASIC functionality designed specifically for SONET/SDH packet processing.

The latter part, the ORSO82G5, has a baud rate of 2.7Gbps and includes a pair of payload processor cores that can convert non-SONET interconnect schemes into SONET/SDH. If desired, designers can bypass the SONET functionality and use the chip's 10,400 available programmable-logic elements to implement their preferred framing techniques.

The third member of the serdes family is Lattice's in-system programmable GDX2, a switching device that is suitable for switched backplanes, board edge connectors, bus multiplexers, and backplane drivers.

Comprised of a global routing pool surrounded by I/O buffers, FIFOs, serdes blocks, and PLLs, the GDX2 chips were designed to translate signals from one electrical interface to another. Depending on the version, users can select 64, 128, or 256 I/Os. The 64- and 128-I/O versions run at frequencies of 330MHz and feature pin-to-pin delays of 3ns; the larger 256-I/O version has a 300MHz operating frequency and a 3.5-ns pin-to-pin delay.

With a baud rate of 0.85Gbps, the serdes of the GDX2 family is less capable than the company's other serdes offerings. At the same time, each serdes channel in the GDX2 implementation costs $2, which is at least $10 lower than the going rate of a high-speed serdes interface, Lattice said.

This should widen its appeal to designers of industrial, medical, and storage systems who want to replace noisy, EMI-prone parallel interconnects with more elegant serial technology, said Gordon Hands, Lattice's strategic marketing manager.

Though serdes technology can simplify board layouts and increase system performance, it requires extensive analog expertise and is considered difficult for chip suppliers to master. Most FPGA vendors import the technology from outside providers.

Lattice acquired its serdes technology last year when it bought the Orca FPGA group from Agere Systems Inc. For its Virtex 2 Pro devices, Xilinx licensed serdes technology from Mindspeed Technologies. Altera Corp., meanwhile, is set to announce its latest serdes-equipped Stratix FPGAs next month.

- Anthony Cataldo

EE Times





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