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Velio serdes integrates four OC-48 transceivers

Posted: 29 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:velio communications? serdes? oc 48 transceiver? quad serdes? sonet phy transceiver?

The VC1021S serdes from Velio Communications integrates four OC-48 (2.488Gbps to 2.67Gbps) transceivers into a 27-by-27mm, 352-pin BGA and is designed specifically for SONET/SDH PHY layer applications.

Based on the company's GigaCore serial I/O technology, the serdes converts four different interfaces of 4x622MHz LVDS I/O, with clock, to a set of four independent 2.488Gbps to 2.67Gbps CML streams, to support both OC-48 and FEC-encoded OC-48 data rates. The VC1021S has a typical power consumption of 2W - half that of four discrete OC-48 transceivers.

The device includes extensive SONET/SDH processing features such as SONET/SDH frame alignment of up to 235 bytes; SONET/SDH scrambling/descrambling; arbitrary byte insertion/monitor; LOF, LOS, SEF, B1, B2 monitors; and K1, K2, D1, D2, D3, J0, M1 byte insertion/monitor.

The VC1021S is sampling today and is available in volume shipments in December. Pricing starts at $99 each in quantities of 1,000.

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