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Net processor suppliers to brace for long shakeout

Posted: 29 Oct 2002 ?? ?Print Version ?Bookmark and Share

Keywords:network processor? applied micro circuits? linley group? netlogic microsystems? asic?

A long shakeout lies ahead for network processor makers, a senior chip executive predicted at the Network Processor Conference West, even as some startups launched their first products and others in attendance were not yet ready to announce any products or plans.

"I do not think the consolidation will be over until 2005. There is a long way still to go. And I am afraid 2003 will be worse than 2002 was," said Doug Spreng, member of the board of Applied Micro Circuits Corp. (AMCC), in a keynote at the net processor conference. "There is too much R&D money going after too little revenue at both the system and chip levels," said Spreng, who recently retired as president of AMCC, one of a few NPU makers that analysts said may survive the shrinkage in telecom carrier spending.

Indeed, analyst Linley Gwennap, principal of The Linley Group, has estimated that as much as $1 billion has been spent, largely in venture capital, to support a market that is now believed will grow to just $1 billion to $1.5 billion by 2005.

Gwennap said that among established companies he expects only AMCC and Intel Corp. to survive the NPU shakeout. Long-term success is doubtful for NPUs from IBM and Motorola, he added. Among startups, he said, EZchip Technologies and Silicon Access Networks Ltd could stay the course, the latter in part because it has secured a whopping $120 million in financing. Other startups will fail during the next two years, however, as their money dries up, Gwennap predicted.

Skewed investments

Analysts noted that investment trends have become hugely skewed. Jag Bolaria of Linley Group said that search engine designer NetLogic Microsystems Inc., for example, has netted $90 million in financing to date, despite the fact that the market for search engines in 2001 totaled only about $70 million. At best, that market segment, now pursued by about a dozen chipmakers, is projected to grow to $300 million by 2005, Bolaria said.

Keynoter Spreng said he thinks startup chip and systems makers will feel the brunt of the shakeout, but telecom OEM giants like Nortel Networks and Lucent Technologies, while struggling mightily now, will survive. "The carrier relationships there are very well established. They will find a way," he said.

In the wake of the carrier collapse, Spreng said, chipmakers should focus on supporting the ATM and frame relay infrastructure used by the surviving regional Bell operating companies and expect to transition to Internet Protocol and other, newer protocols. Programmable designs, he added, will suit such carriers' three- to seven-year system-product life cycles.

Debate over ASICs

Spreng predicted that telecom equipment makers are at the start of a long-term shift from ASICs to off-the-shelf chips. Such a transition will likely fuel a return to 50 percent growth rates for NPU makers after 2005, he said. "The ASIC time-to-market process is becoming too long and costly for OEMs. This is a sea change," Spreng said. "Cisco, Nortel and others have NPU evaluation councils now, while Alcatel, Marconi and Lucent already have made their decisions, and the conversion processes away from ASICs are well under way" at those companies.

Although chipmakers accounted for nearly all the conference attendees, a handful of engineers from Nokia Networks took issue with Spreng's view that OEMs are abandoning ASICs. "We don't see that trend. We use whatever is best for the particular application," said one engineer who builds edge routers and asked not to be named. What's more, the engineer noted, buying an NPU instead of ASICs merely shifts the design headache to the software realm. Indeed, the process of learning to program an NPU and developing driver software for it can be as long and complex as developing an ASIC, said analyst Bolaria, who helped set up a software driver program at Intel.

Despite the debate, several companies, startups and established ones alike announced new NPUs at the conference. IBM discussed its second-generation NP4GX, a 500MHz chip with integrated search engine capabilities. Agere Systems Inc. showed off its APP550 Payload Plus, a two-piece chipset that includes an OC-48 NPU and separate traffic manager.

Among the newcomers, IPFlex Inc. unveiled a reconfigurable chip based on a proprietary 32-bit RISC core comprising 1,048 separate arithmetic-processing and memory elements to handle a number of networking jobs. And Teradiant Networks Inc. introduced a family of packet and traffic engines that scale from 10Gb to 40Gb processing and use what the company called a configurable pipeline.

Several stealth-mode startups including Aarohi Communications Inc., Siliquent Technologies, and FlowStorm Inc. attended the event even though they were not prepared to divulge details of their work. "We are getting financing and waiting for the right time," said FlowStorm chief Mario Nemirovsky.

Standards progress

On the standards front, the Network Processing Forum (NPF) announced details for a streaming interface with versions that link NPUs to each other, to framer chips and to switch fabrics. The 16-bit LVDS interface is compatible with SPI 4.2.

The forum is also defining a messaging-layer protocol for all its hardware interface standards. Rather than join the fray of control plane interfaces defined by microprocessor vendors, however, the NPF plans to provide NPU requirements based on its messaging work to interface developers like the HyperTransport Consortium, the RapidIO Trade Association and others. "Standards help us reduce the number of interfaces we have to support and thus our pin count and thus cost," said Russell Dietz, chairman of the NPF's hardware working group.

Finally, the forum said it has finished its first version of an NPU benchmark suite that measures IPv4 packet-forwarding performance. Forum members said they hope three or four vendors publish results based on the benchmark by the end of the year. The forum is also developing a benchmark for switch-fabric chips and is adding IPv6 and multiprotocol label switching tests to its original benchmark.

Building on the forum's work, The Linley Group launched its own benchmark. The LinleyBench 2002 will require results across two ports and a specific set of interfaces to facilitate comparisons between chips. LinleyBench also includes DiffServ tests with Layer 4 classification and support for 100k route tables. The NPF benchmark only requires 30k tables.

"We think that more closely reflects real routing tables today," said Bob Wheeler, senior analyst at The Linley Group.

A version of the benchmark will be released next year that measures performance on packet ordering, scheduling, and traffic management.

To date only IBM has shown results based on the new benchmarks. At the conference the company distributed a 15-page report of its first-generation NP4GS3 on the LinleyBench. AMCC said it is working on benchmarks but had to modify its reference design to accommodate the 100k route tables required to run them. Intel said it will have some benchmarks published by the end of the year.

"We foresee developing more application-specific benchmarks in the future," said Wheeler.

- Rick Merritt

EE Times

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