Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Synthesis-friendly RTL called key to first-pass design

Posted: 08 Nov 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lsi logic? asic? rtl design? physical design? soc?

To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line message delivered by LSI Logic Corp.'s director of ASIC technical marketing, Jeff Vanderlip, in a presentation at the EE Times-sponsored SoC Online Conference.

Vanderlip said the first step in the design process - creating the chip architecture - can have the biggest impact on whether a design will make a smooth run through physical design. A good architecture can have a 40 percent impact on timing improvements, he said. But no competent tools exist to automate architecture design with physical design in mind, Vanderlip said. Thus, most companies must rely on experienced architects to ensure an architecture is physical-design friendly.

RTL creation and coding is the second biggest factor that will determine whether a design will speed though the design process, Vanderlip said. Coding RTL so that it runs properly in physical synthesis can account for a 20 to 40 percent improvement in timing, he said.

RTL code that is not optimized for use in physical synthesis can cause many problems, Vanderlip said. LSI Logic has seen instances where physical synthesis has not recognized critical paths or structures because of improper coding. That leads the physical synthesis tool to generate a sea of gates, which in turn are distributed by a placement engine through an entire chip design when physical synthesis does not recognize a path or structure for what they are, Vanderlip said.

Such errors burn up man-months because they force designers to go back to the RTL coding, and sometime to the architecture, to fix problems, Vanderlip said.

He endorsed the use of proper coding guidelines - the creation of synthesis-friendly RTL - to ensure a smooth, speedy designs.

"A proper synthesis approach is absolutely the key to providing efficiency for the placement and physical-synthesis tools," Vanderlip said. "There are two aspects to this. The first is to follow common sense, good practice synthesis guidelines, but another is to understand the proper synthesis approach to use for key modules in a design."

In the future, Vanderlip said designers will have to provide a greater amount of physical design information when handing over designs to ASIC vendors.

"Today, clocks in a physical planning flow are implemented, then ripped up and reimplemented in final layout," said Vanderlip. "Moving forward, final clocks will need to be implemented during the physical planning stage."

Crosstalk, signal electromigration, manufacturing and yield issues will all need to be addressed in the design planning stages, Vanderlip said.

"Physical synthesis and physical prototyping tools will need to develop physical RTL analysis and optimization capabilities," he continued. "Today we have two disjointed solutions where you have physical RTL optimization flows and you have separate physical synthesis and planning flows. RTL optimization flows are rule-based and dependent on the rules set. Physical synthesis and planning are gate-level netlist based - they are limited in optimization potential. More importantly, they have no trace back to RTL problems."

- Michael Santarini

EE Times

Article Comments - Synthesis-friendly RTL called key to...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top