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Synchronization, timing put on one chip

Posted: 26 Nov 2002 ?? ?Print Version ?Bookmark and Share

Keywords:9co? scs 30xx? vcxo ic? ocxo ic? tcxo ic?

The latest synchronization and timing solution from 9Co combines all of the timing-selection, phase lock, synthesis, and control functions in a single-chip device.

The SCS-30xx series chips require only an external 12.8MHz OCXO/TCXO as the primary frequency generator, a VCXO plus DAC converter for the output synthesizer, and an E2PROM to store the holdover data, the company said. The SCS-3010 and SCS-3015 meet Telcordia General Recommendations GR1244, GR253 and international standard ITU-T-G813.

The digital PLL, implemented with 9Co's Nova Kernel (a set of algorithms and control), is the heart of the chips. Key features include predictable and repeatable digital frequency and phase lock performance using direct digital synthesis techniques, complete hitless switching, holdover history management and control, and fine-grain phase buildout for reference switches.

The devices accept up to eight external reference signals from 8kHz to 77.76MHz, as well as a cross-couple 8kHz input for master/slave operation. The frequency offset error threshold is selectable in increments of 0.1ppm up to 110ppm.

All reference inputs are monitored for signal presence and frequency offset error, and reference selection is achieved directly by the application or automatically by the company's algorithms.

Internal-priority and signal-integrity driven, the Nova Kernel operates revertive or nonrevertive, on a per-reference basis. Direct control is made via hardware or a bus interface program control.

The analog PLL control block with the external voltage-controlled oscillator and D/A provides the output frequency from 8kHz to 77.76MHz. A separate digital frequency synthesizer generates a 1.544MHz or 2.048MHz bits clock output in the SCS-3015. The control block interfaces external application controls with the internal operations and parameters of the chip.

Other features include free-run clock calibration capability and individual reference input monitoring for loss and frequency offset. The total broadband jitter performance is <200ps peak to peak and jitter performance for the SONET frequency band is 3ps rms.

The SCS-3010 chip is available in a BGA, a 144-pin package or as a complete module, including the OCXO, DAC, and VCXO. An evaluation kit is available. Pricing is $95 each in lots of 1,000, with delivery of stock to eight weeks, depending on quantity.

EE Times

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