Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Amplifiers/Converters
?
?
Amplifiers/Converters??

Nanoimprint lithography ready to make its mark

Posted: 26 Dec 2002 ?? ?Print Version ?Bookmark and Share

Keywords:nanoimprint lithography? molecular Imprints? nanonex lithography tools? scanning electron microscope? obducat?

A potentially low-cost form of lithography affectionately known as "squish and flash" by its backers is coming to market.

Three vendors have announced or released tools for the technique, properly known as nanoimprint lithography. And the concept has garnered enough interest among research entities in the U.S., Europe, and Japan.

Imprint lithography uses polymers that harden into patterns when exposed to ultraviolet light through a 1:1 proximity mask. The patterns on the template are written with an electron-beam system at the same line width as the pattern on the wafer, rather than at the 4x reduction possible with conventional optical lithography.

Molecular Imprints Inc. (MII) next month will ship a development tool, the Imprio 100, with a $2 million price tag, said CEO Norm Schumaker. Nanonex Corp. is shipping nanoimprint lithography tools that range in price from $300,000 to $700,000. Scanning electron microscope manufacturer Obducat AB also plans to field a nanoimprint machine.

Imprint lithography is relatively inexpensive because it avoids costly optics, as well as cumbersome enhancement techniques like phase-shift masks. The machines cost far less than today's step-and-scan systems.

MII, which is a spinout from the University of Texas at Austin, has worked closely with Motorola Inc.'s corporate research lab in Tempe, Arizona, on development of templates. There is speculation that Motorola might be MII's first client, but Schumaker declined to identify customers.

One unidentified customer of Princeton University-backed Nanonex is using its system to make optical devices, said Stephen Chou, the company's founder and an electronic-engineering professor at Princeton. And a team at Princeton has used a Nanonex system to fabricate MOSFETs at sub-100nm dimensions.

Broad efforts

In the U.S., much of the early nanoimprint lithography research at Harvard, Princeton and elsewhere has been sponsored by the Defense Advanced Research Projects Agency (Darpa) and the Office of Naval Research. Meanwhile, research consortia in Europe and Japan are funneling money into nanoimprint lithography development efforts, many of which were detailed at the inaugural Nanoimprint and Nanoprint Technology (NNT) conference.

That meeting, held in San Francisco this month, attracted an international group of 200 researchers, revealing surprisingly broad efforts into a form of lithography that more closely resembles wax seal embossing than the photographic exposure systems in widespread use today.

In a sense, imprint lithography hearkens back to the early days of contact printing, with two essential differences: Contact printing relied on the wavelength of light to define the circuit patterns, and the masks that came into contact with the silicon wafers.

Imprint lithography does not depend on optical elements; rather, the line width is determined solely by the template, which is separated from the wafer by a lubricant: an off-the-shelf monomer. Exposure to ultraviolet light releases free radicals in the monomer that attack the double-bond pairs to form a cross-linked polymer, which hardens, much like exposed photoresist, into a pattern.

The comparison with wax breaks down quickly because the monomer is a low-viscosity liquid, much like water, spreading easily across the template. The template acts as a mold that is lowered onto the lubricated wafer with a few pounds per square inch of pressure.

The volume of liquid is extremely small: Only a few nanoliters (a few millionths of a liter) are required for each pattern. A few tablespoons of the monomer can be used to process 2,500 eight-inch wafers.

According to participants at the NNT conference, Chou's group at Princeton stunned the lithography community in 1997 by demonstrating patterns of 10nm dimensions. But for semiconductors, which often require more than 20 built-up layers, the problem is in the alignment of the layers. Both Nanonex and MII currently spec the alignment of their first-generation machines at 500nm, or 0.5?m, while cutting-edge semiconductors require layer-to-layer alignment of 50nm to 100nm.

"Alignment is the key issue," Chou said. "At Nanonex we see our way to improving on that because we have a special way to press the mold on the substrate. We do not use direct mechanical arms to press," he added, declining to be more specific.

"With imprint lithography you can make the patterns as small as you want," Chou said. "CD [critical-dimension] control is automatically better than photolithography. But we have to solve the alignment issue by pressing the mold without rotation." Nanonex claims to be a turnkey supplier that teaches customers how to create the templates using a converted scanning electron microscope developed at Princeton.

Low-pressure system

The competitive juices are flowing at suppliers and research labs, as engineers figure out ways to optimize the key steps in imprint lithography. MII's CTO, S.V. Sreenivasan, a mechanical-engineering professor on a two-year sabbatical from U.T.-Austin, said he and MII co-founder Grant Willson, a polymer chemist at UT-Austin who developed photoresists during a long career at IBM Corp., have devised a room-temperature, low-pressure imprint system that does not require the high temperatures used in earlier imprint systems.

And MII has developed an inkjet-like microdispenser that applies the monomer liquid on the area just prior to the lowering of the template. The imprint-and-step function takes about 20 to 30 seconds per field, improving throughput.

The company is applying for patents on its method of stopping the flow of the monomer just at the edge of the area to be patterned, Sreenivasan said. He declined to describe the method until the patents are filed.

Schumaker, a former Bell Labs researcher who has worked at several equipment companies, said MII "is not trying to be all things to all people. Initially we will go after MEMS [microelectromechanical systems], biodevices, the thin-film heads used in hard-disk drives, packaging and the 3D-type patterns with four or five levels, like the stair-stepping structures used in optical devices."

Boosting throughput

Many photonic devices are created using direct-write electron-beam machines, which can take up to an entire day to pattern one wafer. Imprint lithography is a means of enhancing the throughput of e-beam, Schumaker said, by using the time on the e-beam machine to scribe the pattern on a template. The template can be used in an imprint machine like MII's Imprio, which can process several wafers per hour.

Sreenivasan believes that by fully integrating the dispense and imprint steps, the throughput will be boosted to about 30 wafers/hour, from five or six now. And as more-precise mechanical components are developed - including the leveling "flexure" subsystem to position the template - alignment can be improved to chip industry standards.

To develop a production-worthy system, MII is working with corporate partners, including Motorola, KLA and Lam Research as well as DuPont Photomasks and Photronics, which would supply the commercial-use templates.

Eventually, Schumaker said, imprint lithography will be applied to low-volume ASICs. But that day will not come until large amounts of money can be raised to create tools with sufficient alignment accuracy. MII and Nanonex each have raised about $12 million thus far.

"One advantage of our approach is that the circuit designers need not be stifled by the demands of optical proximity correction, which can limit how you place the patterns," Schumaker said. "And for devices like a microlens, an optical-grating coupler or a HEMT [high-electron-mobility transistor] device, what might take five or six steps in optical lithography can be done in one step with imprint. We can pattern on top of a grating, for example, and other surfaces with severe topological features. That has advantages as MEMS enter the nanoelectronics realm and become NEMS."

Far removed

Indeed, imprint lithography is being applied to myriad applications that are far removed from conventional semiconductor manufacturing. At the NNT conference, Harvard professor George Whitesides described how the technique is being used to create dots on biodevices. Clusters of breast cancer cells, for example, are grown on each dot. Then, cancer-fighting drugs can be tested by applying various doses of the medicines and measuring how the cells respond.

Yong Chen, a staff member at the Hewlett-Packard Laboratories in Palo Alto, California, described a vision of molecular electronics in which circuits are scaled down to nanometer dimensions. "In our lab, a process has been invented to use molecules with bistable electronic properties to fabricate high-density molecular devices and circuits," said Chen.

Imprint lithography was used to create metal electrodes with sub-50nm dimensions. Langmuir-Blodgett molecular thin films with switchable electronic properties were sandwiched between the electrodes. The HP lab has developed an electronically addressable crossbar memory circuit with an astoundingly high density of 6.4Gb/cm?.

Stanford professor W.R. Fabian Pease described at NNT how a form of imprint lithography was used to create a gene chip at Affymetrix Corp. "To make a gene chip we need enormous contrast - levels of contrast that would require 80 layers with conventional lithography," Pease said in his NNT keynote.

- David Lammers

EE Times





Article Comments - Nanoimprint lithography ready to mak...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top