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ACAD fields hybrid power analyzer

Posted: 27 Dec 2002 ?? ?Print Version ?Bookmark and Share

Keywords:acad? finepower? soc design? simulator? power analyzer?

Combining gate-level dynamic analysis with static or "semi-dynamic" transistor-level analysis, ACAD Corp. is rolling out FinePower, a tool that checks power and IR drop for SoC designs. The company claims they have found a new technology that significantly speeds the analysis while maintaining accuracy.

Although founded in 1997, ACAD has kept a low profile and has not made previous public announcements. The company has been selling TurboSpice, a fast circuit simulator, and an earlier version of FinePower that only offered gate-level analysis. All of the company's current customers are located in Asia or Europe, said Andy Huang, ACAD's president and founder.

Huang was a VP at Epic Design Technology before its acquisition by Synopsys Inc., and later ran Asian sales for Synopsys' Epic tools. ACAD has 22 employees and has received around $4 million in investment capital, Huang said.

The most significant aspect of the new release of FinePower is its "hybrid" combination of gate-level and transistor-level analysis, Huang said. "Our customers are doing SoCs with embedded memories and analog parts, and for those portions, they really need a hybrid engine to give them much more accuracy," he said.

For digital logic analysis, Huang said that customers will typically run about 80 percent of the logic at only the gate level. Transistor-level analysis is reserved for specific areas, such as analog or mixed-signal blocks, where a gate-level analysis would involve a "black box" approach, he said.

Huang noted that the transistor-level power and IR drop analysis is not fully dynamic, because that would be too slow. "Semi-dynamic means the customers can input their current waveform in piece-wise linear format," he said. "Then we invoke a matrix solver without doing the full, detailed simulation, and we have the same accuracy level as in TurboSpice."

Next step planned

Huang said that TurboSpice, with its simplified matrix solver, comes within 5 percent of Spice for timing analysis and within 10 percent of Spice for power analysis. TurboSpice itself is not yet integrated with FinePower, but that is the company's "next step," he said.

To speed analysis, ACAD has developed an algorithm it calls Global Peak Searching (GPS). This algorithm focuses on "time regions" that consume more power than others, and uses VCD simulation files to get time and event information for nodes and cells. It identifies the 100 "worst case" nodes, and focuses the matrix solver on these, instead of running through an entire simulation.

FinePower does not need user-defined estimation factors, Huang said. With static, gate-level tools, he noted, users typically have to estimate the relative power consumption of various blocks.

A January release of FinePower will add inductance analysis for off-chip bonding pads and packages, Huang said. ACAD is also working with Silicon Metrics Corp. to get more accurate junction capacitance information for MOS gates, because Synopsys' Liberty library format only provides static leakage current information, he said.

FinePower can be used for pre-layout or post-layout power and IR drop analysis. Input consists of a Verilog netlist, VCD format file, and Detailed Standard Parasitic Format (DSPF) or Reduced Standard Parasitic Format (RSPF) files. For post-layout analysis, it can also read GDSII layout files.

The tool provides a graphical user interface that can display hot and cold areas of an SoC. Working with Synopsys' PrimeTime analyzer, FinePower can also display critical paths graphically. Users can experiment with different ways to reduce power, such as changing the width of a power bus or adding power straps, and then rerunning the analysis. FinePower does not modify the original GDSII file, but offers a report on anything that has changed.

A dynamic, gate-level analysis of around 1 million gates took about 40 minutes in a customer benchmark, Huang said.

FinePower is available now, with time-based licenses starting at $40,000.

- Richard Goering

EE Times





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