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Philips achieves 0.12?m SoC solutions

Posted: 02 Jan 2003 ?? ?Print Version ?Bookmark and Share

Keywords:process technology? cmos? 0.12 micron? 0.13 micron? soc solutions?

Having started manufacturing commercial quantities of complex logic devices on CMOS12, a 0.12?m process technology, Philips Semiconductors has become one of the first silicon players to provide system-on-chip (SoC) solutions at advance process technology.

The firm will be using the same process technology in its recently released Nexperia chips for digital consumer video and multimedia cellphones.

The new process will considerably boost the company's efforts to take full advantage of new growth opportunities that it foresees within the semiconductor industry. Moving from 0.18?m CMOS to 0.12?m achieves a factor of two reduction in die size and corresponding reduction in chip cost. At the same time, the smaller transistors on the chip operate faster and consume less power, which means that CMOS12 chips outperform their 0.18?m counterparts in every respect.

Smaller die size and lower power consumption also allow less expensive IC packages to be used, while the higher integration density of CMOS12 means that more of the customer's system can be implemented in a single chip, reducing component count, cutting assembly costs and furthering equipment miniaturization.

Philips Semiconductors claimed in a statement that these chips were 'right-first-time' in terms of design, which together with the quality of the 0.12?m CMOS process, meant that the first chips off the production line met all performance specifications.

"We put a great deal of effort into ensuring that the design rules were consistent with achieving a high yield when the process came on-stream this year," said Rene Penning de Vries, Deputy Chief Technology Officer, Philips Semiconductors. "That provided us with high confidence levels when we migrated our 0.18?m cell libraries to 0.12?m, enabling us to put a comprehensive suite of design libraries and tools quickly into the hands of our chip designers."

Smart alliance

Meanwhile, Philips Semiconductors' alliance with Motorola, STMicroelectronics, and TSMC seems to be on track. The cooperation would save the purchase of unnecessary equipment and relieve some of the pressure to reduce the ranks of skilled manpower.

It started two years ago as pressures to accelerate programs to remain at the forefront of IC fabrication-led companies to look past its doorstep for potential partners. To accelerate developing process technology for deep-submicron ICs, the three chip giants pooled resources to share the risk of process development for ICs below 0.1?m.

The agreement does not include, however, collaborating on fabrications facilities. De Vries said, "We share elements which do not differentiate us from our competitors. Even if we share a lot of building blocks with our partners because we feel that it is an efficient way to share the huge costs of developments, each company still decides for itself in adding options special to them. So is the case in the design environment and library - we only share designs that we feel will help our competitive position."

- Denice Obina

EE Times - Asia





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