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Direct digital synthesizers cut power by 90 percent

Posted: 09 Jan 2003 ?? ?Print Version ?Bookmark and Share

Keywords:Analog devices? ad9858? add9951? ad9952? ad9953?

Analog Devices Inc. has released a direct digital synthesizer (DDS) family that cuts power consumption by 90 percent over previous versions through the application of patent-pending algorithms and the migration to a 0.18?m process.

Targeting communications, instrumentation, and radar applications, the family clocks at 400MHz, synthesizing frequencies up to 160MHz while consuming <200mW.

Used instead of a PLL in applications where fast frequency hopping and precise phase control are required, the DDS allows the creation and manipulation of sine waves in the digital domain. "One of its main claims to fame is its fast frequency-hopping capabilities, which allow you to change frequencies in one clock period," said Jim Surber, a marketing communications manager at ADI's RFIC Division. "They also add the element of ultra-precise tuning of that frequency, up to 232 of the output frequency."

Communications applications, according to Surber, include use of the device as a local oscillator for the tuning function, "as it can easily be put under processor control in the digital architectures that communications systems are moving toward anyway." Other applications include broadband networks, quadrature upconverters, and transmitters. "Radar is a natural application because of its chirp capability [the device can readily output a swept frequency]," Surber said.

Despite their advantages, direct digital synthesizers are notoriously power-hungry, and because the analog output is generated via a DAC, they are typically limited to 40 percent of the fundamental frequency. In the case of ADI's new AD995x family, operating at 400MHz, the output is limited to 160MHz.

"We keep pushing the clock frequencies up and the power consumption down," said Surber. For example, the company's current 1GHz chip, the AD9858, consumes 2W when clocked at 400MHz, vs. the 200mW of the AD995x family. Also, the AD9852 and 54, which have been out for a number of years, clock at up to 300MHz and dissipate 2.2W. "So, we are talking about a 90 percent reduction in power," said Surber.

The power reduction was achieved through the migration to a 0.185m process and modifications to the algorithms used for the output-signal calculations, said Ted Harris, applications engineer with ADI's clock and signal synthesis group.

Calculations on the fly

"We do not use the typical lookup table," said Surber. "We have an algorithm that calculates the phase angle on the fly, so we refined that calculation process." While the device operates off 1.8V, it does include separate 3.3V supply rails at the output to allow backward compatibility with current designs.

Other features of the family include an integrated 14-bit DAC, on-chip 125-element RAM, phase-offset and amplitude control, and multichip synchronization.

The synchronization feature is a bragging point for ADI's clock and synthesis group and is a direct result of customer feedback, said Harris. "One of the problems we have come across is that when designers try to include multiple signals in the same system [as in a quad upconverter], they find the parts accurate with 32-bit control over frequency and phase - but with respect to what? How do they know they are starting at the same instant?"

To date, ADI has advised customers to match up their reference clock lines and digital-data lines so that signals arrive at the digital components at the same time. "But all we could offer was a synchronous reset, which left them flat," said Harris.

With the synchronous output of the AD995x line, the DDS generates a synchronizing signal that can be supplied to devices throughout the system. "There is also a synch input, so you can have a master/slave relationship, with each knowing their respective phases," said Harris.

That function is very useful in quad upconverter designs where the designer needs to know that the inputs in the analog modulator are in quadrature, since even a slight phase deviation would result in local-oscillator (LO) feedthrough, said Harris.

"With this device, once the two products are synched and set at the same frequency, you can set the I channel and gradually tweak the Q channel and so adjust for temperature variations, etc.," he said. "You can supply what the analog modulator needs for LO feedthrough cancellation. That is a function that has not appeared in these DDS chips before."

With the integrated a 14-bit DAC, multiple DDS chips can be placed on a single board without a thermal problem, said Surber. "This allows a new application in synchronized multiple DDS [devices] to get synchronized clocks out."

Smaller pack, faster port

The ability to pack multiple devices on one board is helped by the move to a 48-lead QFP from an 88-lead device - a switch that also cut power consumption. But the smaller package meant dumping the parallel port, said Surber. As a result, the AD995x line compensated by pushing the serial port from 10Mbps to 25Mbps.

The AD9951 ($13.75) is a basic DDS with on-board 14-bit DAC; the AD9952 ($15.50) includes a high-speed comparator; the AD9953 ($14.75) has RAM for nonlinear phase/frequency sweeping; and the AD9954 ($17.25) includes a high-speed comparator, RAM and an automatic linear frequency sweep function.

All devices are sampling now, with production scheduled for March.

- Patrick Mannion

EE Times





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