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The genesis, success of 64-bit MIPS - an Embedded Perspective

Posted: 15 Jan 2003 ?? ?Print Version ?Bookmark and Share

Keywords:processor? processor core? intel? amd? dram?

Tom Riordan

VP and GM, MIPS Processor Division, PMC-Sierra

Today, 64-bit addressing is becoming more and more prevalent as witnessed by the recent introduction of competing 64-bit processors by Intel and AMD. Moreover, the use of the 64 bits for data manipulation turned out to be an immediate hit in the emerging high performance networking market. Taken all together, the desire for 64-bit addressing, a 64-bit wide data cache to feed a 64-bit floating-point unit, a clean 32-bit RISC architecture easily extendable to a backward-compatible 64-bit architecture, and a belief that the resulting architecture could last for many decades made a compelling case.

A new process generation, that of 0.25?m, was on the horizon and it was time to consume yet more transistors. The analysis that showed the roll off in CPI improvement with increased cache size, you can see that the stall length affects where this roll off occurs. If DRAM speeds increased at the same rate as processor speeds, this would not matter since the length of the stall would remain a constant when measured in processor cycles. For various reasons too detailed to address here, DRAM speeds do not keep up with processor speeds instead, only the increase in number of DRAM bits tends to track the increase in processing speed - Moore's law says only that the number of transistors will double not that the speed will double. As a result of DRAM speeds not keeping up, engineers started building second level caches external to the processors and for a while this mitigated the processor-DRAM speed discrepancy. It was only a matter of time, of course, before it became possible to increase performance by integrating the second level caches. In the quarter micron generation it was possible to economically build a processor with 16KB primary instruction and data caches and a 256KB second-level cache.

In addition to the integrated second-level cache, these processors included another performance enhancement: the transistor gobbling technique known as superscalar. Superscalar techniques had been widely tested and reported on during 1H of the 1990's, and the cost/benefit ratio for various degrees of parallel instruction issue was pretty well established. For the power and cost-sensitive embedded market, it looked reasonable to implement a simple two-way superscalar pipeline that would give a 25 to 30 percent performance boost with about the same percentage of additional hardware and complexity.

The new 64-bit processor, first built in 0.25?m and now in 0.18?m and 0.13?m technologies, has been a phenomenal success in both the networking and printer markets and is expected to move into the consumer market in the near future.

The latest 64-bit MIPS, as might be inferred from the "x2" designation, contains not one but two 64-bit processors each with integrated second level caches, targeting at the networking infrastructure market and having an integrated DDR memory controller and a very high speed HyperTransport I/O link. The processors, memory, and I/O are all connected via a packetized crossbar to achieve a high-performance, fully cache coherent silicon system. In addition to providing increased system performance via parallel processing, the performance of the individual processors is improved by incorporating both the superscalar and "superpipelining" techniques. The 64-bit processor core of the x2 will be used extensively within solutions requiring high-performance processing such as networking, printer, and consumer ASSP's and CSSP's.

Today, PMC is shipping 64-bit MIPS architecture processors in high volumes and, as Moore's Law marches relentlessly on, the cost/performance ratio will become increasingly attractive. Through the symbiotic relationship of MIPS Technologies, PMC-Sierra and other MIPS licensees like Broadcom, NEC, Toshiba, etc., the 64-bit MIPS architecture will continue to grow and our customers will be able to take advantage of the benefits of 64-bit processing.





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