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TAEC SoC doubles gate integration

Posted: 21 Jan 2003 ?? ?Print Version ?Bookmark and Share

Keywords:Toshiba America electronic components? taec? tc300? cmos4? soc?

Toshiba America Electronic Components Inc. has launched its 90nm TC300 family of SoCs based on the company's CMOS4 process technology.

Employing 11-layers of copper wire and low-k insulating material, the TC300 delivers about a 100 percent increase in gate integration, a 20 percent increase in gate speed, and a 50 percent reduction in power consumption, compared to the previous generation 0.13?m process technology.

The CMOS4 build-on-modular process permits easy mixing of mixed signal, DRAM, and application specific IP on the same chip. It supports logic densities of up to 400,000 gates/mm?.

The TC300 is targeted at next-generation, high-end applications ranging from high-speed intensive networking and server applications to digital multimedia devices that manage A/V information and portable wireless devices that require low-power consumption.

It operates from a 1.2V and has 1.8V-, or 2.5V-, 3.3V-tolerant I/Os. Gate delay is typically 9.5ps, while power consumption is 7nW/MHz/Gate. The TC300 is available with an SD or FA type DRAM. The SD type DRAM has a maximum clock cycle of 300MHz, supports 9.6GBps data transfer rate, and has a maximum I/O width of 256 bits. The FA type has a random access time of up to 8ns and a maximum I/O width of 288 bits.

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