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Leakage current called obstacle to chip complexity

Posted: 12 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:semiconductor chip? international solid-state circuit conference? takayasu sakurai? moore law? chip complexity?

The semiconductor industry must reduce leakage current in chip designs by two orders of magnitude over the next 10 years, or face an interruption in projected chip complexity, University of Tokyo professor Takayasu Sakurai told the International Solid-State Circuits Conference in the U.S. Today's approaches to the problem are only getting the industry half way home, and the solutions to handle the rest of the job have not been invented yet, said Sakurai, a former chip designer for Toshiba Corp.

Addressing the 50th ISSCC's theme of "power aware systems," Sakurai said failure to address leakage current could make the problem "the big stumbling block to Moore's Law."

Gordon Moore, the co-founder of Intel Corp. who coined Moore's Law - which posits that chip complexity will roughly double every 18 months - also spoke of leakage current in a plenary address at ISSCC on Monday. Leakage current is set to overtake active power consumption as the chief villain in the battle against wasted power, Moore said.

Double-gated and triple-gated structures, as well as high-k gate insulators, will be needed to stem the rising tide of leakage current, Moore said.

Looking at the leakage current problem when supplying energy to portable systems, Sakurai said researchers are working to transmit energy to such systems wirelessly. Power can be transferred to an electronic system from vibrations in nature, or from the heat generated by human hands, Sakurai said.

To reduce leakage current, designers can insert into chips device-level switches, which turn off current to a block of logic. Using the thick oxide layers required for analog circuits, the switches would completely cut off leakage current in certain portions of a chip.

By designing a chip to have just two levels of power, or Vdd, large amounts of power can be saved. Transmeta Corp., with its Crusoe processor, has many levels of supply voltage, but Sakurai said that such an approach can increase testing costs. Use of only two levels of supply voltage - one for normal operation, and a higher voltage that is called into play when speed is needed - can reduce active power consumption considerably, Sakurai said. He played a video that showed power consumption in an MPEG-2 decoder being reduced by throttling back voltage during portions of the decoding process, even as video quality was maintained.

"When you don't have to hustle, relax," Sakurai advised.

Back-gate approach

Many companies are using back-gate bias control to reduce standby power consumption. This approach uses the substrate, or back-gate, as a fourth terminal in MOSFETs, which are normally considered three-terminal devices. Intel uses back-gate bias to reduce power consumption in its Xscale microprocessors, and Hitachi Ltd. uses it in its SH line of 32-bit controllers.

In long-channel CMOS, Sakurai said, the prevailing view was that threshold voltage was fixed for each transistor. In short-channel devices, researchers are coming to understand that threshold voltage can be varied by modulating drain voltage. This phenomenon, known as drain-induced barrier lowering (DIBL), is not easy to control but remains promising, Sakurai said.

Companies and universities in Japan have been working hard on the power consumption issue, Sakurai said in an interview following his keynote address. A catch phrase in Japanese, tan sho kei haku (short, small, light and thin), describes the type of systems Japanese companies have been trying to perfect, including cellphones, digital cameras, PDAs, and other portable systems.

"Leakage could become the limiting factor at the 65-nm node and beyond," Sakurai said. To find new solutions, "we have to get the software, system design, process technology and circuits people all working together."

- David Lammers

EE Times

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