Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Inductance issues not what they seem at 90nm

Posted: 14 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:inductance? metal interconnect? 90nm? oea int.? inductance analysis tools?

Inductance in metal interconnect will force design teams to deal with a number of new issues as the industry moves toward 90nm line widths, according to executives at OEA Int. Inc., a supplier of inductance analysis tools. But the issues may not be the ones everyone has in mind.

"To begin with, there's the perception that because the lines are so much closer together at 90nm, inductive coupling will be much worse than we've experienced before," said OEA VP of marketing and sales Jerry Tallinger. "That's not the case. It seems plausible, but in fact analysis shows that inductive coupling only becomes an issue when resistance is relatively low - that is, with big, wide traces. At 90nm, the traces are so fine that resistance is becoming an important factor. But that is actually reducing the importance of inductance."

There are situations in which that generalization is not so true, added VP of business development Haris Basit. For instance, when spiral inductors are integrated into deep-submicron processes, you have both big, wide traces and very fast edge rates, coupled, so to speak, with lots of active metal near the inductor. That has led OEA to do an active business in synthesis tools for inductors.

False warnings

Another exception is the upper metal layers, which generally have wider metal and coarser pitches and are used to carry supply, ground and clock signals. In these wide traces, inductance is also significant and must be analyzed. A third area, Tallinger said, is in I/O nets, where once again very fast edge rates and wide interconnect lines mean that lots of current is running around with little resistance.

These exceptions are sufficient to constitute a serious issue in the design flow, according to Basit. "There are relatively simple tools you can use to spot self-inductance problem areas, but even these often give a lot of false warnings. There are no simple tools for mutual inductance.

"But the real problem isn't analysis; it's design planning," Basit said. "If you do a design by putting blocks together and putting an I/O ring around them, you will have too many violations to deal with. You have to incorporate some sense of inductance issues into design planning."

That is a particular problem because the design planning tools that are emerging today tend to ignore inductance altogether, Tallinger said. He added that there are cases where even with good planning, inductance problems can be created by the routing tools during back-end design. But those pale beside the problems that are designed in.

The OEA managers suggested that, until inductance can be more successfully incorporated into design planning tools, a member of the team with a good intuitive feeling for inductance issues - armed with detailed analysis tools - should be incorporated in the design from at least the floorplanning stage. When inductive features are intentionally incorporated, the emphasis should move from planning and analysis to synthesis, which is where OEA's product line fits.

The company offers high-performance 3D extraction, simulation and analysis, coupled with inductor synthesis, in a portfolio of about a dozen products.

- Ron Wilson

EE Times





Article Comments - Inductance issues not what they seem...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top