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Samsung eases into MRAM memory race

Posted: 14 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:samsung? magnetoresistance ram? mram? memory?

Samsung Electronics eased into the race to perfect magnetoresistance RAM (MRAM), unveiling its research aimed at relaxing the tight tolerances required for tunneling oxide thickness.

The Korea-based memory maker joins a host of other companies, including Cypress Semiconductor, IBM, Infineon Technologies AG, NEC and Motorola, Inc., who are looking into MRAM as a universal replacement for SRAM, DRAM, and Flash devices. Motorola seems to be leading the race and is expected to sample a device this year and release a 4Mb device for embedded systems sometime in 2004.

Before MRAM becomes an overnight sensation, it must surmount a few significant obstacles, one of which is manufacturability in a high-volume fab. Even extremely slight variations in the oxide, on order of 0.1?, can change the magnetic tunneling junction (MTJ) resistance by several percentage points, making the device unpredictable.

However, consistently keeping within the required oxide thickness in a real-world fab environment is tough, especially across an 8-inch wafer. "The most serious problem is the resistance variations but this can be handled with a self-reference sensing scheme, said Gitae Jeong, Samsung's lead researcher on the approach.

Using a 16Kb test chip as proof, Samsung believes its sensing scheme will make MRAM relatively immune to oxide variations in the manufacturing process because each cell will have its own reference point that is pinned to its individual oxide thickness. Neighbor cells could have different values and it would not significantly affect the operation of the MRAM array; indeed Samsung reported that tunneling resistance varied by 2.5 ohms to 11 ohms.

Furthermore, Samsung offered some details of its test chip. During the program cycle, Samsung converted MTJ resistance into voltage and stored it in a capacitor. After storing, the free layer of the MTJ cell was magnetized so it's parallel to the pinned layer. That state is also assigned a value by a similar conversion and storage scheme.

During readout, these two stored voltages are sensed and amplified by the sense amplifier. If the first stored voltage is lower than the second one, it is a 0; if the first voltage is larger than the second, it is a 1. A drawback, noted by Jeong, is that the read process is destructive so data must be reprogrammed to the main cell.

- Mike Clendenin

EE Times





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