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Bridging optical and Ethernet

Posted: 17 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:flexible bridging? bridging technology? optical network? ethernet? fpga?

With network investments in a lull, infrastructure spot renovations are more common than teardowns and rebuilds. These spot upgrades are melding new technologies with legacy infrastructure and creating a need for linking leading-edge high-speed technologies with legacy protocols.

This creates situations not yet defined or approved by an industry standards body. Fixed solutions are ill-equipped to handle these situations, as they have neither sufficient intelligent glue logic nor the field-upgradability to incorporate a newly approved standard. For example, engineers are faced with the challenge of how to rapidly mesh ubiquitous Ethernet LANs with long-haul optical links and high-bandwidth network processors that use the System Physical Interface 4 Phase 2 (SPI-4.2).

Through the use of flexible bridging technologies, the existing optical infrastructure can support today's data-heavy traffic patterns. These bridge designs strive to use as much existing technology, protocols, interfaces, chips, and intellectual property (IP) as possible. And a FPGA-IP core can add the final touches such as packet framing, jumbo packet support, flow control, and remote system configuration. Ultimately, this technology leveraging extends the existing infrastructure life span and allows new features without overly taxing unavailable corporate investment.

One common example is the need to connect Ethernet to Sonet. As 10GbE is not yet commonplace, we will consider an interface between an OC-192 (10Gbps) SONET port and 10 ports of GbE. On the Ethernet side would reside a GbE transceiver and a GbE-MAC. The MAC completes the PHY to link-layer conversion and presents the data through an SPI-4.2 interface. On the Sonet side is an optical transceiver and an optical framer. This also presents an SPI-4.2 interface, but there is significant bridging technology needed between these two SPI-4.2 interfaces.

An FPGA is best suited for housing this bridging technology. The level of wire-speed throughput required demands we use an FPGA or ASIC implementation, rather than a CPU or DSP. The upgradable feature requirement and the ASIC's high upfront cost, determines our choice should be an FPGA.

Continuing with the desire to use off-the-shelf technologies wherever possible, look for a vendor with a standard design for the packet-over-SONET Level 4 interface (POS-PHY), which is the basis for the SPI-4.2 standard. Interfacing the two POS-PHY cores can require custom FPGA-IP core development for key areas such as packet framing, jumbo packets, and flow control.

Look at the packet framing. Two major submodules need to be designed within the FPGA core. An Ethernet-to-Sonet multiplexer handles the multiplexing or interleaving of packets in the ingress direction. A Sonet-to-Ethernet demultiplexer handles the egress direction where packets are redistributed to the correct port.

During the multiplexing process, two important factors must be considered. First, while combining multiple Ethernet ports into a single Sonet port, an additional routing header must be inserted. This header contains the destination port ID, and is used on the demux side to route the packet to the appropriate port.

Second is managing running disparity, which requires that an even number of ones and zeros be transmitted to avoid a dc offset that can lead to corrupted data on fiber. Both of these concerns are addressed with the use of the generic framing procedure. This procedure establishes a standard method for adding an additional routing header and the 8-bit to 10-bit data conversion to manage running disparity.

- Michael Worry

CEO and CTO

Nuvation Engineering Inc.





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