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Velio chip supports backplanes at 6.25Gbps

Posted: 20 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:velio communications? gigacore2? sonet ic? xaui ic?

Velio Communications Inc. has sampled a test chip that implements the company's 2G I/O core, used for switching fabrics, serdes, and repeater devices. GigaCore2 supports backplane speeds of 6.25Gbos, while maintaining compatibility with 3.125Gb and slower interfaces.

The test chip can be used immediately in custom designs under development at OEMs, the company said. Velio also plans to implement the new core in a variety of devices slated for release late this year, including a grooming switch supporting full SONET interfaces and an interleaver device that supports XAUI optical interfaces for GbE.

Ramesh Senthinathan, director of technology development, said that Velio ensured backward compatibility with older serial-interconnect technology by eschewing specialty modulation, such as pulse-amplitude modulation, instead retaining non-return-to-zero encoding. Typical power dissipation for the core is 130mW at 6.25Gbps, which Senthinathan said is unprecedented in serial-interface designs.

Variety of signal conditioning

The transmitter block in GigaCore2 offers three types of pre-emphasis signal conditioning. Pre-emphasis on transmit can reduce crosstalk and noise, and attenuate low-frequency components of the signal, the company said, while an equalizer implemented on the receive block can alleviate the effects of intersymbol interference. In the test chip, four channels of transmit and receive are implemented.

Custom design starts using the core are being taken now, and Velio plans to sample some of the products built around GigaCore2 by mid-year.

- Loring Wirbel

EE Times





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