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Altera enhances Nios processor memory, software

Posted: 20 Feb 2003 ?? ?Print Version ?Bookmark and Share

Keywords:altera? nios processor core? risc processor? fpga processor? stratix processor core?

Altera Corp. has packed a new version of its homegrown Nios processor core with enhanced memory, debugging, and software capabilities. At the same time, the company has rolled out new tools and a hardware kit for the RISC processor used in its FPGAs.

To give designers an alternative to expensive off-chip SRAM, Nios now sports an SDRAM controller that can do pipelined data transactions exceeding 100MHz. Altera tweaked its Avalon switch fabric - also called a parameterized bus interface - to accept those transactions through the use of posted-read and posted-write operations. Designers can also decide how much instruction and data cache the Nios should have - anywhere from 1KB to 16KB for each.

For software developers, Nios now has real-time debug capabilities via a JTAG core from First Silicon Solutions Inc. The core supports in-circuit emulation features like hardware triggers and real-time trace.

A second component is the Codelab development environment from Mentor Graphics Corp.'s Accelerated Technology division, which allows engineers to edit, compile, download, and debug their Nios code. Users must buy the software directly from Accelerated Technology.

The full Nios development kit also contains a library of Ethernet protocol software. Altera promises to update the software components regularly over the Web through its SOPC Builder tool.

Updates of hardware IP cores, custom Nios instructions, debuggers, and OSs will also be done in this manner, the company said. The first Nios development kit for Altera's high-end Stratix FPGA is priced at $995.

Altera plans to come out with a 2G Nios architecture later this year.

- Anthony Cataldo

EE Times





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