Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Summit tool beefs up SystemC

Posted: 03 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:visual elite 3.1? fastc? systemc? hdl code? verilog?

Promising to make it easy for RTL designers to step up to the SystemC language, Summit Design Inc. released a new version of its Visual Elite system-level design tool. Visual Elite 3.1 includes FastC, a SystemC simulator that offers direct mapping to synthesizable HDL code.

Summit Design is also extending its involvement with the SystemC standards effort. Meanwhile, the company said it is setting up a sales office in Silicon Valley. The company is based in Burlington, Massachusetts, but most of its employees work at Summit's R&D facility in Herzlia, Israel.

Summit's Visual Elite tool began its life by converting graphics into synthesizable HDL code, but recently, it has grown to encompass SystemC. Previous versions included a SystemC 2.0 simulator. However, FastC, which accelerates a subset of SystemC, offers the best way to reach out to HDL designers, said Moshe Guy, Summit's president and CEO.

"We want to provide a smooth path for the HDL user who wants to move to SystemC but is afraid to adopt a new methodology," Guy said. "FastC code is close to Verilog. Someone familiar with RTL code can learn FastC in maybe half a day."

Guy said FastC contains the synthesizable subset of SystemC. It can run those constructs 10 to 300 times faster than any HDL simulator. Thus, designers can accelerate their synthesizable SystemC code with FastC while running nonsynthesizable code on Summit's full-fledged SystemC simulator, he added.

Moreover, FastC allows co-simulation with any HDL simulator, allowing designers to run Verilog or VHDL alongside SystemC.

Visual Elite 3.1 also offers new support for virtual prototyping, said Guy. That is because users can create a design in SystemC and generate a virtual prototype that contains the Fast hardware simulator. This prototype can then be handed to software designers so that they can begin code development.

FastC supports the hardware modeling of bidirectional ports, tristate resolved values, and advanced wait statements for testbenches. Visual Elite 3.1 includes a built-in hardware/software communications interface and instruction-set simulation.

Meanwhile, Summit is participating in the further development of SystemC as part of the Open SystemC Initiative, which promotes SystemC as a system-level design language. Yossi Vaeller, Summit's chief technical officer, will join the SystemC behavioral synthesis and verification committees, Guy said.

- Richard Goering

EE Times

Article Comments - Summit tool beefs up SystemC
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top