Synopsys technology enhances TI ASIC design flow

Texas Instruments Inc.'s (TI) ASIC division has completed two multi-million gate designs using Synopsys Inc.'s Physical Compiler, a central component of Synopsys' Galaxy Design Platform. In addition, TI has now integrated Physical Compiler into its standard Pyramid ASIC design flow.

The Physical Compiler, a key component of Synopsys' Galaxy Design Platform, enables the design of high performance circuits on an accelerated timeframe. By unifying synthesis and placement, the Physical Compiler is designed to offer designers a faster path to timing closure.

"Working with Synopsys' Physical Compiler increased our productivity, improved performance and accelerated turnaround times for these high-end complex IC devices," said Steve Sutton, VP of TI ASIC Division. "The inclusion of Synopsys' Physical Compiler into our standard Pyramid ASIC methodology gives our customers a clear path to taking advantage of TI's advanced silicon processes."