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Cadence verification platform has unified methodology

Posted: 05 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? incisive verification platform? incisive xld? incisive vld base? verification tool?

Cadence Design Systems Inc. has launched its Incisive verification platform, which it claims to be the first single-kernel verification platform for nanometer-scale designs that supports a unified verification methodology for the embedded software, control, data path, and analog/mixed-signal/RF design domains.

The unified methodology helps slash testbench development time, verification runtime, and debug time, thus compressing overall verification time by up to 50 percent. This boosts the time-to-market for semiconductor customers and accelerates system design-in of complex ICs for design chain partners.

The Incisive platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, property specification language PSL/Sugar, algorithm development, and analog/mixed signal. It also combines an extensive transaction-level environment with fast, unified test generation, and the company's Acceleration-on-Demand capability.

The platform includes the Incisive simulation-based, digital verification solution; the Incisive-XLD simulation-based verification for up to 10 engineers; and the Incisive-VLD Base that includes an accelerator/emulator base unit and delivers up to 10,000 times performance improvement.

The Incisive-XLD delivers Acceleration-on-Demand, which gives design teams the runtime option of using up to 10 seats of Incisive, or up to a million gates of acceleration capacity. The acceleration is hosted on a local or remote multiuser Cadence Palladium accelerator/emulator, which can deliver 100 to 10,000 times the performance of simulation. This capability allows design and verification teams to work interactively during the day and run up to a billion verification cycles overnight.

The unified methodology begins with an architecturally accurate, transaction-level Functional Virtual Prototype (FVP). Transaction-level FVPs can run 100 times or more faster than equivalent RTL, making them more suited for architectural performance analysis, early embedded software verification, and early system design-in. FVPs also provide a fast, full-chip environment for block-level verification.

Within a domain, the unified methodology supports top-down and bottom-up approaches. When block-level verification is complete, FVPs serve as the vehicle for integrating verified blocks and running full-chip implementation-level verification with Acceleration-on-Demand.

The Incisive verification platform is available immediately on HP, Sun, IBM, and Linux platforms. Specific operating-system support varies by product. The platform also includes the Cadence NC family, Cadence SPW, Cadence AMS Designer and Cadence Palladium.

Cadence Design Systems is an exhibitor at the International IC-China (IIC-China) Design & Exhibition show running from March 3 to 11 at Shanghai, Beijing, and Shenzhen. It is co-located with the Embedded Systems Conference - China and are both organized by eMedia Asia Ltd, a Global Sources and CMP Media joint venture.





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