Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Interra upgrades memory design tool

Posted: 06 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:interra systems? mc2? memory development system? memory design tool? discrete memory design?

Interra Systems Inc. has added several automated features to its MC2 Memory Development System for Discrete and Embedded memory designs.

The latest version of the tool, according to Anand Desai, Interra's VP of engineering, automates the overall methodology for the design and distribution of memories, helping designers create solutions more rapidly while reducing development time by over 40 percent, claimed Desai.

Sridhar Gangadharan, Interra's senior manager of EDA operations, said the latest version of the tool automates a number of tasks that in previous versions had to be completed manually.

"MC2 gives you an automated framework which takes care of the complete process, all the way from the design of the leaf cells, stitching the cells to the time you actually tapeout your memory," said Gangadharan. "In addition, it automatically generates all the functional views necessary for any memory instance."

Users input data about their memory design using the Memory Design Language. They also can enter leaf cell information and memory templates and can use the tool's new automated characterization feature or enter the data manually.

The tool then employs a number of engines to perform various tasks including leaf cell tiling, netlisting to create schematics for LVS, timing, and power calculation for characterizing models, model generation, and ROM personalization.

Gangadharan said the tool automatically generates physical views GDSII and LEF, as well as logical views with LVS, SPICE, and Verilog. "The tool also generates a complete characterization of the memory and feeds the characterized data into Verilog or Synopsys models and produces tapeout documentation in the form of datasheets," said Gangadharan.

MC2 starts at $70,000.

- Mike Santarini

EE Times





Article Comments - Interra upgrades memory design tool
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top