Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Controls/MCUs
?
?
Controls/MCUs??

ARM, Cadence ink five-year design chain optimization deal

Posted: 07 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:arm? cadence design? ip core? verification tool?

ARM Ltd and Cadence Design Systems Inc. have entered into a five-year agreement under which ARM will provide direct access to ARM intellectual property to facilitate optimization of design and verification solutions from Cadence's design and verification solutions on ARM core-based SoCs.

The cooperation between ARM and Cadence will enable customers to incorporate different ARM cores into the recently launched Cadence Incisive verification platform for high-speed verification. As a result, customers are expected to be able to build systems with verified, reusable hardware and software IP blocks faster and with greater confidence that the systems can be manufactured the first time. The two companies are currently working on improving design chain interoperability via standardized models and validation suites for ARM's AMBA bus using the SystemC modeling language.

Planned deliverables of this collaboration include Cadence Incisive verification tools combined with the ARM Integrator Logic Tile products for acceleration/emulation, and Cadence signal integrity solutions combined with ARM signal integrity libraries for specific foundries. The results will benefit systems designers such as architects, hardware verification engineers and software developers, fabless designers and integrated device manufacturers (IDMs).





Article Comments - ARM, Cadence ink five-year design ch...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top