Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Telairity, Icinergy find synergy

Posted: 07 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:telairity? Icinergy software? soc? planning tool? asic?

Fabless ASIC vendor Telairity Corp., whose technology is based on the use of pre-hardened macro blocks, and Icinergy Software, a maker of SoC planning tools, announced that Telairity would use Icinergy's SoCarchitect as part of its recommended flow.

The move combines two entirely different approaches toward the same goal: maintaining greater abstraction throughout the SoC design process. In this way, it may move at least some categories of SoC designs closer to the ideal of never having to deal explicitly with physical implementation.

Telairity's ASIC offering is based on an extensive library of parameterizable macroblocks. These blocks are in effect medium-sized pieces of hard IP, pre-optimized for a particular process, and adhering to rigorous rules as to contact location, scanability and functional composition. The macroblocks are chosen to be the most complex possible elements from which larger digital circuits can be constructed without loss of generality.

In theory, a designer would compose the digital blocks in an SoC out of combinations of these macroblocks, very much like decomposing the design into a block diagram. Because of the way the macroblocks are defined, the resulting design would be correct by construction with regard to global routing, signal integrity, power and clock distribution, and the other headaches that take up the majority of the time in physical design.

Yet because the macroblocks are individually optimized, and because the library is rich, the theory goes, the design would at least approach the compactness and performance of a full-up cell-based design.

Into this picture SoCarchitect fits as a front-end tool. The Icinergy product has received compliments from users for its ability to support floorplanning and give useful information about resource use and routing even before RTL exists for all the blocks in the system. Presumably, SoCarchitect used in conjunction with the Telairity libraries would provide a direct path from initial estimated floorplan to macroblock layout to completed physical design, without any explicit RTL code having been created.

- Ron Wilson

EE Times

Article Comments - Telairity, Icinergy find synergy
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top