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Ikanos selects Tharas tool for chip verification flow

Posted: 10 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:ikanos communications? tharas systems? broadband? design verification? hammer?

Broadband access vendor Ikanos Communications Inc. has incorporated Tharas Systems Inc.'s Hammer into its functional verification flow. Tharas' Hammer provides Verilog, VHDL, and mixed language accelerated simulations with compile and run times claimed to be the fastest, while offering ease-of-use and debug capabilities comparable to that of software simulators.

"Ikanos evaluated competing hardware acceleration solutions and found that Hammer offers the fastest compile time and met our acceleration expectations over software based solutions. Fast compile times are very important to us, as during the development stage, RTL changes are frequent.," said Anoop Khurana, VP of Engineering at Ikanos. "We plan to run a lot more simulation cycles in our multichip system simulation environment with the Hammer solution."





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