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Spreadsheet tool generates HDL interfaces

Posted: 12 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:matrixhdl? vhdl coding tool? hdl coding tool? vhdl tool? verilog tool?

Consultant Douglas Perry developed a spreadsheet tool to simplify his own HDL coding work, and found it so useful that he started a company, MatrixHDL, to offer it to other designers for $99. The tool, also called MatrixHDL, lets users enter interface descriptions and automatically generate VHDL or Verilog.

With MatrixHDL, engineers describe entity-architecture modules and their interconnections in a spreadsheet format, and the tool generates VHDL or Verilog descriptions from the spreadsheet file. "It's a very handy tool for specifying a very concise description of the interfaces of an HDL-based design," said Perry.

The $99 price tag will hardly fund a major EDA startup, but that's not Perry's goal. "I'm not really trying to make any money with it, just to try and recover hosting and maintenance costs," he said.

Perry said he created the tool in 1999 after working with a number of clients and realizing that it was tedious to create the interface code of the blocks in the design. "Most of the data for the interface code is exactly the same," he said. "The differences are module names, port widths or types and port directions. So it seemed reasonable to just capture this information in a concise format."

What came out of this effort, he said, was a spreadsheet with module and entity names across the top, and signal and port names across the left. Users fill in whether the signal is connected to a module, whether it's an input or an output and how big or what type it is. Users can make incremental changes to the interface and generate HDL throughout the project, Perry said.

MatrixHDL is available for download from the MatrixHDL web site. Perry said that support for SystemC and SystemVerilog is next on his list.

- Richard Goering

EE Times

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