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NEC expands silicon platform for high speed interfaces

Posted: 14 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:nec electronics? instant silicon solution platform? issp his? serdes core? issp architecturem cell based asic?

NEC Electronics has expanded its 0.15?m Instant Silicon Solution Platform (ISSP) with the addition of two new base arrays offering up to 1.5 million usable gates and 3.7Mb of embedded configurable memory, and a 3.125Gbps serdes that supports high-speed interfaces including XAUI, InfiniBand, PCI Express, GbE, and Fibre Channel.

The ISSP architecture combines the benefits of cell-based ASIC design with customizable upper layers to meet the individual design requirements and produce cost-effective, high-performance devices with fast turnaround times, the company said.

The high-density base arrays are available in versions that offer up to 1.5 million usable gates, up to 900,00 internal registers, and up to 2.5Mb of embedded configurable memory; or in another configuration that supports 1 million usable gates and 3.7Mb of embedded configurable memory.

On the other hand, the company has also released a new ISSP high-speed interface (ISSI-HSI) family that incorporates the company's serdes core. The core supports data rates of 3.125, 2.5, 1.25, and 1.062Gbps, as well as 622Mbps to meet specific application requirements. It dissipates 220mW/channel at 3.125Gbps.

The ISSP-HSI devices incorporate four or 16 serdes channel cores to support multirate applications. Operating at clock speeds of up to 250MHz, the devices have densities of up to 1 million usable gates, 70,000 internal registers, and 2Mb of embedded configurable memory. They have an internal supply voltage of 1.5V and interfaces to 2.5V and 3.3V I/O sources. Other features include four embedded analog PLLs and eight to 32 DLLs.

Along with the release of the ISSI devices, NEC Electronics has collaborated with Synplicity Inc. to optimize the Synplify ASIC synthesis software with custom mapping technology to support the ISSP architecture.

The company has also worked with Tera Systems Inc. to develop an ISSP-optimized RTL rule checking and planning tool that secures timing closure and physical implementation at the RTL design stage.

ISSP designers also have access to NEC Electronics' OpenCAD design framework, which includes physical floorplanning, timing-driven layout, and hierarchical design. The ISSP architecture also supports hardware/software co-simulation/co-verification on a block-based system design approach.





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