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Startup pushes shared-memory switch scheme

Posted: 17 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:terachip inc.? tcf16x10? switch fabric ic? ic component design? mindspeed technologies?

Despite facing a tough market, startup TeraChip Inc. will come out of the gate this week with its first product, a switch-fabric IC. The TCF16X10 employs shared-memory architecture and delivers an aggregate 160Gbps switching capacity on-chip.

TeraChip traces its roots to IC Component Design, an Israeli design services house that developed custom ICs for DSP, radar, and VPN applications, said TeraChip CEO Michael Zeiger. After working on the development of an ATM switch, Zeiger, then head of IC Component, and his team saw a "horizon" in the Internet Protocol-switch market and morphed the former design services operation into a commercial chip player in November 2000. Just over two years later - with $18.5 million in funding raised - the company has moved its headquarters to the West Coast and has developed its first IC.

So how will TeraChip stand out in an already-crowded market? VP of marketing Dror Sal'ee said that the answer lies in the chip architecture. Many switch-fabric backplanes on the market today have been developed using a crossbar fabric, requiring an off-chip scheduler to control the movement of data across the backplane. The scheduler has been one of the big challenges for the traditional crossbar approach, Sal'ee said. "The scheduler has been tough to build," he said. Additionally, the scheduler requires tight synchronization between the switch and line cards, he added.

Some companies, including Mindspeed Technologies, have tried to solve crossbar problems by putting queue managers on switch-fabric cards. "This comes at a price," Sal'ee said. "Building these cards could require up to 24 components on the fabric card. That's very expensive and requires a lot of power."

TeraChip takes a different stab at the problem with shared-memory architecture. TeraChip embeds an SRAM on its fabric device to switch traffic. Zeiger said data received from a port is immediately sent to the SRAM. With information from the traffic manager, the SRAM then switches, determining which output port to send the packet to. Once the port has been determined, the packet is sent to the output port, where it is queued up for transport out across the system. "The memory is a switch," Zeiger said.

The TCF16X10 provides 16 ports; each supports 10Gbps data rates to create a total chip aggregate throughput of 160Gbps. Additionally, each port on the chip is equipped with a queue engine that can support eight priority levels.

The TCF16X10 will target LAN, SAN and MAN applications.

The chip, developed in a 0.135m process at TSMC, delivers 15W power dissipation figure.

- Robert Keenan

EE Times





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