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Xilinx DSP tool reduces simulation times

Posted: 21 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? system generator for dsp? dsp design tool? dsp simulation? matlab?

Xilinx Inc. has announced the availability of the System Generator for DSP tool v3.1, which adds hardware-in-the-loop and HDL co-simulation capabilities to enable designers of DSP to reduce simulation time and cut development costs.

The tool is designed to automatically translate DSP systems using The MathWork's MATLAB and Simulink tools into VHDL and IP cores for Xilinx FPGAs. The hardware-in-the-loop capability accelerates the design cycle by allowing users to verify designs in hardware directly from the Simulink environment in real-time.

The company claims that when running hardware-in-the-loop using a free running clock, designers are capable of achieving up to six orders of magnitude improvement in simulation speed.

HDL co-simulation allows users to import legacy HDL code and provide hardware designers with system level modeling capability. The HDL co-simulation interface allows designers to reduce development costs and time by automatically invoking Mentor Graphics' ModelSim tool directly from Simulink and co-simulating HDL code together with Simulink models.

Additionally, the new DSP tool enables designers to model the DSP system control functions through MATLAB M-Code, Boolean expressions, and Xilinx's PicoBlaze soft microprocessor, thereby steamlining the design process by incorporating data and control capabilities into a single environment.

The new System Generator for DSP v3.1 is available now for use with Xilinx Virtex and Spartan Series FPGAs and is priced at $1,995.





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