Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Averant enhances proprietary assertion language

Posted: 25 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:averant? solidify? formal verification tool? hpl language? open verification library?

In a new release of its Solidify formal verification tool, Averant Inc. claims to have significantly enhanced its HPL property specification language. The new release also claims improvements in automatic cone reduction, automatic checking, and hierarchical verification.

With Solidify 2.8, the company said the HPL allows better complex patterns expression and monitor creation. These features support tasks such as packaged bus verification.

Further, the Solidify 2.8 features an improved automatic checking system that lets users run checks on multiple CPUs. The new release adds an "array over bound" check for Verilog and a dead code check for VHDL.

Solidify 2.8 also expands a hierarchical capability that verifies failing module properties at high levels. So if a property passes at a higher level, the designer immediately knows that a failure has occurred at the lower level.

Solidify 2.8 will be available in April.

- Richard Goering

EE Times

Article Comments - Averant enhances proprietary asserti...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top