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Automation tool speeds physical-design flow

Posted: 26 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:reshape? gds builder? physical design tool? channel less block? hierarchical chip construction?

Design services firm ReShape Inc. will introduce a physical-design-automation system this week that it claims will let designers turn around production layouts of multimillion-gate SoC in 24h.

ReShape's president and CEO, David Gregory, who co-founded Synopsys Inc. in 1987, said he has been waiting to find the next big boost in design automation and that he believes ReShape's GDS Builder represents "the biggest breakthrough in production since logic synthesis was introduced 20 years ago."

Among engineers using the same physical-design tool suites, "those with advanced methodologies get so much more performance out of them," said Gregory. "Since I left Synopsys, I've been looking for a way to capture advanced designer know-how and advanced methodologies and to automate the physical-design process."

Physical design is amenable to automation because the tools have well-defined inputs and outputs, he said.

GDS Builder was initially developed within Silicon Graphics Inc. but was purchased by ReShape co-founders Paul Rodman and Margie Levine in 1997 for use in ReShape's design services work. ReShape said it has refined the technology based on input from users to craft a commercial tool and methodology.

GDS Builder automates much of the communication among popular physical-implementation tools from Synopsys, Cadence Design Systems Inc. and Mentor Graphics Corp. The system preserves and automates a point-tool flow, letting users put together a design flow using best-in-class tools from multiple vendors.

The tool uses a hierarchical chip-construction process that taps ReShape's patented Action-Oriented flow to build design blocks in parallel on Linux servers. A technique called channel-less block abutment is employed to achieve small die size, low latency and high signal integrity.

"In the ReShape flow, engineers manually input a gate-level netlist, an I/O map, timing data, and a floorplan," said Rodman, ReShape's CTO. The tool runs placement and routing automatically, incorporating specialized cells to create an optimum design, he said. It can automatically drive electromigration, power, timing, signal integrity, formal, and DRC/LVS verification tools. It outputs GDSII and some HTML reports.

"Users don't have to be familiar with the nuances of a particular tool," said Rodman. "They simply indicate what reports they want the tool to run, and then it does the verification and returns a Web report. Users can also run these early in the process to iron out any issues at the beginning of the flow."

Early customers have completed nine multimillion-gate IC designs with the technology, ReShape said. The company claims GDS Builder will cut the time needed to complete a first chip from the typical eight to 12 weeks down to less than two weeks, and will cut full-chip build time to 24h, producing a higher-performing design that uses 10 percent to 30 percent less die space than one completed without the tool.

GDS Builder runs on Linux Red Hat 7.3 32-bit and Sun Solaris 8 64-bit OSs. Prices vary according to configuration.

Gary Smith, chief EDA analyst with Gartner Dataquest, said ReShape is one of six companies offering automated flows to power users but one of only two offering commercial tools (the other is Ammocore Technology Inc.). "It is a needed technology, and both ReShape and Ammocore have hot technologies."

- Michael Santarini

EE Times





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