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EDA/IP??

90nm design flow is seen as a community effort

Posted: 27 Mar 2003 ?? ?Print Version ?Bookmark and Share

Keywords:international symposium on quality in electronic design? isqed? transistor asic? eda tools?

Yields for ICs with geometries below 100nm may not exceed 50 or 60 percent, according to Pallab Chatterjee, president of tool integrator SiliconMap and organizer of a panel at the International Symposium on Quality in Electronic Design (iSQED).

Maintaining acceptable yields for 20- to 50-million transistor ASICs will be a severe challenge for design flows and require an extraordinary degree of coordination between SoC designers, foundries, and third party IP suppliers.

"Just getting a design from 'point A' to 'point B' will be a major challenge," Chatterjee said. "Forget about importing third-party intellectual property [IP] and packaging models," he said privately, "I have clients [major SoC developers] who can't get an IP from building 1 to building 3 on their own campus."

The IP transfer and block integration process is much worse for anything analog, confirmed Dennis Monticelli, a technology fellow at National Semiconductor. "Analog is notorious for its demands on physical design, particularly noise, thermal coupling, and device matching," said Monticelli.

Knowledge of design blocks resides with experts within product groups, rather than within a central IP library, and the available EDA tools seldom provide an adequate level of simulation.

The EDA tools - the dozen or more point tools that make up a complex flow - are typically asked to validate the design assumptions that go into a poorly-characterized IP, Chatterjee complained. But even the assumption that the tools are good at what they do may need to be re-evaluated, Chatterjee said.

New power management design concepts such as adaptive voltage scaling (AVS) or adaptive time scaling (ATS) alter the core voltage and clock frequency of a microprocessor, Monticelli explained. "We don't have the tools for this," he said.

Norm Towson, business development VP for silicon integrator Netcell was cynical about the possibilities for moving IP around. New-generation ASICs will likely require 22 separate cells and resemble a "patchwork quilt," he said. "If you use an IP block, you'd better keep his home phone number at hand," he said.

Some 80 percent of design starts never see production, insisted Towson. With the cost of a new IC approaching millions of dollars, IP design teams should be ready for an extraordinary degree of interaction and coordination. "They're all going to be sleeping together under the same roof when the thing gets done," he concluded.

According to PDF Solutions' president and CEO John Kibarian the separation between design and manufacturing is only good through 0.13?m geometries where the yields are in the 50 to 70 percent range, and measures of quality like "contact failures per billion" are on the level of "one or two."

At 90nm geometries, the contact failures per billion must be some fraction less than one - just to maintain the same limited yields. And this won't happen, Kibarian said, without some sort of design-for-manufacturing routine embedded in the design flow.

- Stephan Ohr

EE Times





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