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TEL, Teseda rolls integrated DFT system

Posted: 03 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:tel? Tokyo electron ltd? teseda? design for testability? dft system?

Tokyo Electron Ltd (TEL), together with Teseda Corp., has released an integrated design for testability (DFT) system, which is claimed to lower the cost and time required for wafer testing.

The system consists of TEL's Wafer Probe P-8XL and Teseda's Validator 500 DFT validation tool, and enables wafer tests on semiconductor ICs equipped with DFT circuits, thereby speeding up the test design process and reducing test costs.

Yoshinori Inoue, GM of TEL's Test System Business Unit, believes that, "A wide range of TEL customers are currently using DFT, and it has been proven to provide high test quality and realize time reduction effects."

Steve Morris, Teseda's president and CEO, also added that, "The DFT 'cell-demo' validation system eliminates the need for wafer package cycle latency time."

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