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Tera Systems technology enhances IBM ASIC design flow

Posted: 08 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:tera systems? ibm? rtl silicon virtual prototype? asic design flow?

Tera Systems Inc. has announced that TeraForm RTL Silicon Virtual Prototype (SVP) has been integrated into the IBM Blue Logic MidRange ASIC design flow. The two companies have jointly developed and qualified this flow in support of a new engagement model allowing RTL handoff of customer designs.

TeraForm is used on customer designs upstream from synthesis to identify potential timing, area, congestion and design-closure issues early in the design cycle at the RT-level. The TeraForm-IBM flow delivers predictive analysis allowing early visibility into issues like critical-path timing violations and routing congestion while the RTL is being written, alleviating time-consuming late-stage design iterations.

"IBM's new ASIC design flow with Tera Systems' TeraForm allows customers to increase their focus on functional design, architectural refinement, and resolution of system-level issues instead of low-level design implementation and debug problems," said Alain Labat, president and CEO of Tera Systems.

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