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Safelogic VHDL tool sweetened with Sugar

Posted: 08 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:safelogic? accellera? property specification language? sugar? safelogic verifier 3.1?

New support for Accellera's Property Specification Language (PSL) - based on IBM's Sugar language - is coming from Safelogic, which has announced that its Safelogic Verifier 3.1 product now supports PSL. Safelogic Verifier is a formal property checker for VHDL designs.

Safelogic, a Swedish formal verification company, also claims to have extended VHDL support, and to have dramatically improved its proof and bug search capabilities so users can find corner cases more easily. The Safelogic Verifier works with the company's Safelogic Monitor, a plug-in tool for property simulation.

The promise of PSL is an industry-standard formal property language that allows properties to be shared among tools from multiple vendors. So far this year, Cadence Design Systems, 0-In Design Automation, and TransEDA have all announced support for PSL.

Safelogic first announced its Verifier and Monitor products in October 2002. At the time of introduction, both were based on a proprietary formal property language, but the company said it would move quickly towards PSL support.

- Richard Goering

EE Times





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