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Cadence decries incompatible Verilog versions

Posted: 09 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? eda? verilog? modeling tool? verification tool?

The EDA industry is risking "disaster" with two separate and incompatible versions of Verilog unless the Accellera standards organization quickly hands over SystemVerilog 3.1 to the IEEE, according to Cadence Design Systems Inc. With rival Synopsys Inc. already starting to implement SystemVerilog 3.1, the two largest EDA vendors appear to be taking very different pathways to the next generation of Verilog.

"As we approach Verilog's third decade, there is a distinct possibility it could splinter into more than one language. This could spell disaster for all involved," said Mitch Weaver, VP of marketing of Cadence's functional-verification group, in an EDA Views column appearing at Weaver said that many of the proposed enhancements in SystemVerilog 3.1 are in "direct conflict" with the IEEE 1364-2001 Verilog standard, while others were previously rejected by the IEEE.

"Look, Accellera, get us a timetable and take the [SystemVerilog] extensions and get them immediately into the IEEE," said Stan Krolikoski, VP of Cadence's functional-verification group. "Otherwise we'll end up with implementations from various vendors that don't match the standard Verilog."

SystemVerilog 3.1, a sweeping revision of Verilog that adds high-level modeling and verification features, is currently under review in Accellera technical committees. Dennis Brophy, Accellera chairman, said the Accellera board expects to review the language reference manual by the end of May, at which point SystemVerilog 3.1 will be available for testing and user feedback. While Accellera's intent is to deliver all of SystemVerilog 3.1 to the IEEE for standardization, there's no set timetable, he said.

Brophy said it's important to go through that user-feedback process "without disrupting the IEEE," which, he observed, is still busy with Verilog 2001. He said that Cadence's call to go immediately to the IEEE 1364 committee is "premature," given that System-Verilog 3.1 hasn't even been approved by Accellera yet.

Brophy also insisted that SystemVerilog 3.1 will be fully compatible with IEEE 1364-2001 Verilog, and he said the presence of several members of the IEEE 1364 committee in Accellera's SystemVerilog subcommittees will ensure that any incompatibilities are addressed. But one of those dual IEEE 1364 and Accellera committee members - consultant Cliff Cummings, president of Sunburst Design Inc. - wasn't quite so sure.

Where are the users?

What concerns Cummings is that the Accellera committees are heavily staffed by EDA vendor representatives, with little user participation. "Once it gets over to the more user-oriented IEEE, the users may have different opinions as to which direction the enhancements should take," he said. "There is no guarantee everything in SystemVerilog will make it into IEEE Verilog."

Another IEEE 1364 member who serves on the Accellera committees-Stefan Boyd, president of Boyd Technology Inc.-said there's a proposal from the IEEE 754 standards group that would take Verilog in a "very different direction" from the current SystemVerilog 3.1 proposals. "It is critical that SystemVerilog become the next IEEE 1364 standard. If not, it will diverge - and may need renaming to 'Vera-log,'" he said, alluding to the heavy contributions in SystemVerilog 3.1 from Synopsys' Vera language.

Gary Smith, chief EDA analyst at Gartner Dataquest, said that what's really going on is a "Cadence-Synopsys feud" and that technical details will be worked out. "The timing pretty much depends on how much infighting there is in the technical committee," he said.

There is no apparent disagreement over the need for SystemVerilog 3.1, which provides a higher level of abstraction for modeling and verification, along with testbench generation features and support for assertion-based verification. Cadence fully supports these changes, believes Accellera has done some good work and is trying to "accelerate" the process by getting SystemVerilog 3.1 handed off to the IEEE, Cadence's Weaver told EE Times.

What may have caught Cadence off guard, Cummings suggested, is the fact that so much of the technology in SystemVerilog 3.1 came from Synopsys - including syntax from Co-Design Automation Inc.'s Superlog language and testbench generation and assertion capabilities from Synopsys' Vera language. Boyd observed that many other EDA vendors felt "shut out" of the process, and said "there was little time to consider better proposals."

Krolikoski said there are still a number of incompatibilities between SystemVerilog 3.1 and IEEE 1364-2001, such as the initialization of variables.

Rich Goldman, VP of strategic market development at Synopsys, said that all of the incompatibilities brought up by Cadence in the Accellera committees have been worked on and resolved. "One of the great strengths of System-Verilog is its compatibility with IEEE Verilog. There's a great effort that's been put into that," he said.

Krolikoski also complained of SystemVerilog features previously rejected by the IEEE, such as a "static" key word that makes pieces of code re-entrant. "Why put it back in when we already rejected it?" he asked. "Having to rehash the whole argument again doesn't seem like the right thing to do."

Cummings, however, said he wasn't overly concerned about what appear to be "semiminor" incompatibilities or about features that were previously rejected. "Just because we voted no in 2001 doesn't mean we'll vote no for the next version," he said.

As a result of their differing viewpoints, Synopsys and Cadence are taking very different approaches to SystemVerilog 3.1 implementation. Synopsys isn't waiting, and is already developing SystemVerilog 3.1 support for Design Compiler, VCS and Vera, Goldman said. "We've experienced none of the issues Cadence has mentioned," he said.

But Cadence doesn't plan to support any new version of Verilog until there's an IEEE draft standard, Krolikoski said. "What we're looking for is a rational process for standardization," Krolikoski said. "This is not Cadence versus Synopsys."

Accellera plans to release detailed information about SystemVerilog 3.1 at a Design Automation Conference workshop in June this year.

- Richard Goering

EE Times

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