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Flash memories feature LPC Interface v1.1 compatibility

Posted: 14 Apr 2003 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? flash memory? m50fw016? m50fw11g? firmware hub?

STMicroelectronics has expanded its family of Firmware Hub (FWH) and Low Pin Count (LPC) Flash memory devices with the introduction of two new 16Mb devices, which are compliant with the LPC Interface v1.1 specification.

This allows the M50FW016 (2Mbx8, FWH, Uniform Block) to support multi-byte firmware memory R/W cycles, while the M50LPW116 (2Mbx8, LPC, Boot Block) is able to support R/W cycles. The multi-byte read operation allows the data transfer rate to increase up to 15.6MBps - the fastest among any existing serial Flash interface.

The devices are available in both TSOP40 and PLCC32 packages and are suitable for computer applications such as servers, PCs, and workstations to store system and video BIOS, configuration parameters, and embedded OS. They can also be used to code storage applications in printers, digital cameras, STBs, and DVD-RW drives.

Developed using the company's 0.15?m process technology, they can be electrically erased at the block level and in-system reprogrammed on a byte basis, using a 3V to 3.6V supply. An optional 12Vpp power supply is also provided to reduce programming and erasing times.

The M50FW016 is organized as 32 Uniform Blocks of 64KB each, while the M50LPW116 has asymmetric block architecture: its array of 50 blocks is divided into one boot block of 16KB, two parameter blocks of 8KB, one main block of 32KB, 30 main blocks of 64KB, and 16 parameters of 4KB each.

Typical programming time for both devices is 10?s, with an option to program four adjacent bytes in the memory array simultaneously, through the Quadruple Byte Program command. The erasing time for a 64KB block is 0.75s, although a chip erase operation is also available.

Additional features include a double way for block protection (the first one is hardware, through write protect pins and the second one is software, through lock registers) and the Identification Inputs Pins, allowing up to 16 devices to be connected at the same bus.

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